DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claims
Claims 1, 3, 9, 12, 15 and 20 have been amended.
Claim 7 has been cancelled.
Claim 21 is new.
Currently, claims 1-6 and 8-21 are pending and being considered for examination.
Response to Arguments
Applicant's arguments filed 07/22/2026 have been fully considered but they are not persuasive for the reasons mentioned in the 102 rejections below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 1 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 1 of the instant application.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 2 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 2 of the instant application.
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 3 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 3 of the instant application.
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 4 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 4 of the instant application. Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 5 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 5 of the instant application. Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 6 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 6 of the instant application.
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 8 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 8 of the instant application.
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 9 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 9 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 9 of the instant application. Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 10 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 10 of the instant application.
Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 11 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 11 of the instant application. Claim 12 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 12 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 12 of the instant application.
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 13 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 13 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 13 of the instant application.
Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 14 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 14 of the instant application.
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 15 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 15 of the instant application. Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 16 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 16 of the instant application.
Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 17 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 17 of the instant application.
Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 18 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 18 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 18 of the instant application.
Claim 19 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 19 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 19 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 19 of the instant application. Claim 20 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 20 of U.S. Patent No. 11,929,288. Although the claims at issue are not identical, they are not patentably distinct from each other because claim 20 of U.S. Patent No. 11,929,288 includes all of the limitations in claim 20 of the instant application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ching et al. (2018/0122805).
Re claim 1, Ching teaches a device (Fig. 15B) comprising: first semiconductor layers (338) disposed over a first area (“top area”) of a substrate (210), wherein the first semiconductor layers (338) are separated from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate (Fig. 15B);
a first source/drain feature (254, “left device”) interfacing with the one of the first semiconductor layers (338); second semiconductor layers (438) disposed over a second area (“top area”) of the substrate (210), wherein the second semiconductor layers (438) are separated from each other and are stacked up along the direction generally perpendicular to the top surface of the substrate (Fig. 15B), wherein the first semiconductor layers (338) include a first semiconductor material [48], and the second semiconductor layers (438) include a second semiconductor material [38] different from the first semiconductor material [48];
a second source/drain feature (254, “right device”) interfacing with the one of the second semiconductor layers (438); a first gate structure (366) wrapping around each of the first semiconductor layers (338); and a second gate structure (466) wrapping around each of the second semiconductor layers (438), wherein the first source/drain feature (254, “left device”) extends into the first area (Fig. 15B) of the substrate (210), wherein the second source/drain feature (254, “right device”) extends into the second area (Fig. 15B) of the substrate (210).
Re claim 2, Ching teaches the device of claim 1, wherein the one of the first semiconductor layers (338) is a topmost first semiconductor layer (338) from the first semiconductor layers (338).
Re claim 3, Ching teaches the device of claim 1, wherein the one of the first semiconductor layers (338) is a bottommost first semiconductor layer (338) from the first semiconductor layers (338), and wherein the one of the second semiconductor layers (438) is a bottommost second semiconductor layer (438) from the second semiconductor layers (438).
Re claim 4, Ching teaches the device of claim 1, wherein the first semiconductor material includes silicon [48] and the second semiconductor material includes germanium [38]. Re claim 5, Ching teaches the device of claim 1, wherein the number of first semiconductor layers (338) is equal to the number of second semiconductor layers (438, Fig. 15B). Re claim 6, Ching teaches the device of claim 1, further comprising a sidewall spacer (246) extending from the one of the first semiconductor layers (338) to the first area (“top area”) of the substrate (10).
Re claim 8, Ching teaches the device of claim 1, wherein the first gate structure (366) wrapping around each of the first semiconductor layers (338) includes a first high-k dielectric layer [51] and a first conductive material layer [51], and wherein the second gate structure (466) wrapping around each of the second semiconductor layers (438) includes a second high-k dielectric layer [42] and a second conductive material layer [42].
Re claim 21, Ching teaches the device of claim 1, wherein a bottommost surface (Fig. 15B) of the first gate structure (366) is level with a bottommost surface (Fig. 15B) of the second gate structure (466).
Claim(s) 9-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ching et al. (2018/0122805). Re claim 9, Ching teaches a device (Fig. 15B) comprising: a first plurality of semiconductor layers (338) disposed over a substrate (210), wherein a topmost first semiconductor layer (338) from the first semiconductor layers (338) extends to a first height (Fig. 15B) above the substrate (210); a second plurality of semiconductor layers (438) disposed over the substrate (210), wherein a topmost second semiconductor layer (438) from the second semiconductor layers (438) extends to the first height (Fig. 15B) above the substrate (210); a first gate structure (366) wrapping around each of the first plurality of semiconductor layers (338); and a second gate structure (466) wrapping around each of the second plurality of semiconductor layers (438),
wherein a bottommost surface (Fig. 15B) of the first gate structure (366) is level with a bottommost surface (Fig. 15B) of the second gate structure (466).
Re claim 10, Ching teaches the device of claim 9, wherein the first plurality of semiconductor layers (338) are formed of a first material composition [48], and wherein the plurality of second semiconductor layers (438) are formed of a second material composition [38] that is different than the first material composition [48].
Re claim 11, Ching teaches the device of claim 9, wherein the topmost first semiconductor layer (338) includes silicon [48] and the second topmost semiconductor layer (438) includes germanium [38]. Re claim 12, Ching teaches the device of claim 9, wherein the first semiconductor layers (338) are part of a n-type transistor (nFET) [50] and the second semiconductor layer (438) are part of a p-type transistor (pFET) [40].
Re claim 13, Ching teaches the device of claim 9, wherein a first portion (212) of the substrate (210) directly under the first plurality of semiconductor layers (338) extends to a second height (Fig. 15B), and wherein a second portion (212) of the substrate (210) directly under the second plurality of semiconductor layers (438) extends to the second height (Fig. 15B).
Re claim 14, Ching teaches the device of claim 13, further comprising: a first sidewall spacer (246) extending from the first portion (212) of the substrate (210) to a bottommost first semiconductor layer (338) from the first plurality of semiconductor layers (338); and a second sidewall spacer (246) extending from the second portion (212) of the substrate (210) to a bottommost second semiconductor layer (438) from the second plurality of semiconductor layers (438), and wherein the bottommost first semiconductor layer (338) extends to a second height (Fig. 15B) above the substrate (210) and the bottommost second semiconductor layer (438) extends to the second height (Fig. 15B) above the substrate (210).
Claim(s) 15-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ching et al. (2018/0122805). Re claim 15, Ching teaches a method (Figs. 2B-15B) comprising: forming a spacer feature (220) on a top surface of a substrate (210) between first (left) and second (right) areas (Fig. 2B) of the substrate (210); forming a first stack of semiconductor layers (212, 232, 234) over the first area (left) of the substrate (210) and a second stack of semiconductor layers (436, 438) over the first semiconductor layer (212) disposed over the second area (right) of the substrate (210), wherein the first stack of the semiconductor layer (212, 232, 234) and the second stack of semiconductor layers (436, 438) are proximate to the spacer feature (220) after the forming of the first stack of semiconductor layers (212, 232, 234) over the first area (left) of the substrate (210) and the second stack of semiconductor layers (436, 438) over the first semiconductor layer (212) disposed over the second area (right) of the substrate (210); patterning the first stack (Figs. 12A-15B) of semiconductor layers (212, 232, 234); and patterning the second stack (Figs. 7B-10B) of semiconductor layers (436, 438).
Re claim 16, Ching teaches the method of claim 15, wherein the forming of the first stack of semiconductor layers (212, 232, 234) over the first area (left) of the substrate (210) and the second stack of semiconductor layers (436, 438) over the first semiconductor layer (212) disposed over the second area (right) of the substrate (210) includes alternately forming second semiconductor layers (232) and third semiconductor layers (436) over the first (left) and second (right) areas of the substrate (210).
Re claim 17, Ching teaches the method of claim 16, wherein the second semiconductor layers (232) include a second semiconductor material [46] and the third semiconductor layers (436) include a first semiconductor material [38], the second semiconductor material [46] being different from the first semiconductor material [38].
Re claim 18, Ching teaches the method of claim 15, further comprising removing the first semiconductor layer (232) from over the first area (left) of the substrate (210), wherein the first area (left) of the substrate (210) is exposed after the removing of the first semiconductor layer (232) from over the first area of the substrate (210).
Re claim 19, Ching teaches the method of claim 15, further comprising forming a buffer layer (258) over the first stack of semiconductor layers (212, 232, 234), the second stack of semiconductor layers (436, 438) and the spacer feature (220) prior to patterning the first stack (Figs. 12A-15B) of semiconductor layers (212, 232, 234) and patterning the second stack (Figs. 7B-10B) of semiconductor layers (436, 438).
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re claim 20, Ching teaches the method of claim 19, yet remains explicitly silent to further comprising removing the buffer layer to expose a top surface of the spacer feature; and thereafter, removing the spacer feature.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S BOWEN whose telephone number is (571)272-3984. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/ADAM S BOWEN/Examiner, Art Unit 2897
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