DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Election/Restrictions
Applicant’s election without traverse of Species Aii, Bi, Cii, and Di, claims 21-27, 30, and 33-38 in the reply filed on 2/24/26 is acknowledged.
Claim Objections
Claim 21 is objected to because of the following informalities: where a claim sets forth a plurality of elements or steps, each element or step of the claim should be separated by a line indentation, 37 CFR 1.75(i). Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-27, 30, 33, and 35-37 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Parrish et al. (US 6,550,665 B1) in view of Wang et al. (US 8,240,545 B1).
Regarding claim 21, Parrish teaches:
A method for making a microelectronic assembly [assembly of substrates (201, 203); figures 2A-D], including:
aligning a first bond component [bump (220)] with a second bond component [bump (230)] such that the first and second bond components are in contact with each other [figures 2A-B],
the first bond component being included in a first element [upper semiconductor device comprising substrate (201)] having a first substrate [substrate (201)] defining a first surface and a first conductive element [pad (215)] at the first surface [see figure 2A], the first bond component including a first material layer [one of In, Ga, Sn, Cd, and Bi; 4:59-5:5] adjacent the first conductive element [see figure 2A],
the second bond component being included in a second element [lower semiconductor device comprising substrate (203)] including a second substrate [substrate (203)] defining a second surface and a second conductive element [pad (210)] exposed at the second surface [see figure 2A], the second bond component including a second material layer [one of In, Ga, Sn, Cd, and Bi; 4:59-5:5] adjacent the second conductive element [see figure 2A],
and
heating the first and second bond components to a first temperature above the melting points of the first and second material layers such that at least portions of the first and second material layers diffuse together to form an alloy mass joining the first and second elements with one another [6:60-67].
Parrish does not teach:
the first bond component includes a first protective layer overlying the first material layer;
the second bond component includes a second protective layer overlying the second material layer;
wherein the first and the second protective layers have higher melting points than a melting point of the first material layer and a melting point of the second material layer; and
the first temperature is below the melting points of the first and second protective layers.
Wang teaches an electronic component soldering process wherein a layer of Ni or Cu accelerant (206) is placed onto solder (208) in order to accelerate a solidification of the solder after the heating the solder to the predetermined process temperature and/or to raise the melting temperature of the solder; 1:39-55, 5:21-22, and figure 2.
It would have been obvious to one of ordinary skill at the time of the invention to incorporate the Wang accelerant onto each solder bump in order to accelerate a solidification of the solder after the heating the solder to the predetermined process temperature and/or to raise the melting temperature of the solder. In doing so the accelerant layers would have much higher melting points than any of the Parrish bump materials and thus would not be reached in the soldering process of Parrish. Additionally, the first and second bond components would include the accelerant layers.
Regarding claims 22, 23, and 25, Parrish does not teach:
wherein the alloy mass has a melting point at a second temperature greater than the first temperature;
wherein the first and second protective layers diffuse together and with the first and second material layers during the step of heating to further form the alloy mass; and
wherein the first material layer and the second material layer have lower melting points than an alloy formed with the materials from the first and second material layers and the first and second protective layers.
Concerning any claimed results:
Since the prior art process, i.e. the process based on the combined prior art references above, is identical to the claimed process it is the examiner’s position that the prior art process will achieve any claimed result; such as the alloy mass having a melting point greater than the first temperature. This reasoning applies to any claim below where a result is claimed.
Regarding claim 24, Parrish teaches:
wherein the first material layer includes at least one material component not present in the second material layer before heating [4:59-5:5].
Regarding claim 26, Parrish teaches:
a first material of the first material layer is a different material than a second material of the second material layer [4:59-5:5].
Regarding claim 27, Parrish teaches:
wherein the second material includes tin [4:59-5:5].
Regarding claim 30, Parrish does not teach:
wherein the first protective layer includes copper, and wherein the second protective layer includes at least one of copper or nickel.
However, this is addressed by the incorporation of Wang as noted in the rejection of claim 21.
Regarding claim 33, Parrish teaches:
wherein the first conductive element includes a bulk conductor layer [material of the pad] and a seed layer [Cr or Ti layer; 4:49-58] that overlies the bulk conductor layer, the first bond component being joined to the seed layer [4:49-58 and figure 2A].
Regarding claim 34, Parrish teaches:
wherein a portion of the first material layer diffuses into the bulk conductor layer during heating [this happens in the case no barrier layer is applied; 4:49-58].
Regarding claim 35, Parrish teaches:
further comprising providing a barrier layer [Ni or nitride layer; 4:49-58] between the bulk conductor layer and the seed layer, the barrier layer preventing the first material layer from diffusing into the bulk conductor layer during the heating step [the Ni or nitride layer would achieve this].
Claims 36 and 37 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Parrish et al. (US 6,550,665 B1) in view of Wang et al. (US 8,240,545 B1) as applied to claim 21 above, and further in view of Applicant’s Admitted Prior Art (AAPA) and Fujinaga et al. (US 7,452,798 B2).
Regarding claim 36, Parrish does not teach:
wherein the first substrate is a first support material layer defining the first surface of the first element, and wherein the first conductive element is a metalized via extending through a portion of the first support material layer, the method further including forming the first bond component over the metalized via by depositing the first material layer within an opening of a resist layer that overlies the first surface of the first element, the opening being aligned with the metalized via.
Concerning the claimed structure:
AAPA teaches a first substrate with a first support material layer defining the first surface of the first element, and wherein the first conductive element is a metalized via extending through a portion of the first support material layer, the method further including forming the first bond component over the metalized via; figures 1A-C.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the structure of AAPA into Parrish in order to form a desired electronic device or to incorporate the device of AAPA into Parrish in order to form a desired assembly.
Concerning the depositing:
Fujinaga teaches forming multi-layer solder layer (31) over a metalized surface wherein a photo resist (9) is used to only expose a desired area in the metalized layer for further processing; figures 3A-3F. The examiner also notes the use of a photo resist to layer a substrate is well-known in the art due to the fact that is routinely used.
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Fujinaga into the prior art method in order to create the desired bond component layers, structure, and size.
Regarding claim 37, Parrish does not teach:
wherein the step of forming the first bond component further includes depositing the first protective layer within the resist layer opening.
As noted above Fujinaga teaches multiple layers can be deposited using the photo resist layer. Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention that the photo resist would allow one to deposit as many layers as desired and to also deposit the protective layer in this manner to save time, control size, and/or because it is a known method of layering.
Claim 38 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Parrish et al. (US 6,550,665 B1) in view of Wang et al. (US 8,240,545 B1), Applicant’s Admitted Prior Art (AAPA), and Fujinaga et al. (US 7,452,798 B2) as applied to claim 36 above, and further in view of Savastlouk et al. (US 2005/0133930 A1).
Regarding claim 38, Parrish does not teach:
positioning a seed layer between the first surface of the first element and the resist layer prior to depositing the first material layer within the opening and further overlying an end surface of the metalized via,
depositing the first material layer over the seed layer within the opening, and
removing the resist layer and portions of the seed layer that are uncovered by the first material layer.
Concerning the positioning and depositing:
Fujinaga teaches seed layer (3) is positioned between the surface of substrate (20) and photo resist (9), solder (31) is deposited over the seed layer in an opening in the photo resist, and the photo resist is removed; see figures 3C-E.
Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Fujinaga into the prior art method in order to create the desired soldering component.
Concerning the removing of the seed layer:
Savastlouk teaches making a via wherein seed layer (430.1) is placed under photo resist (440) during the manufacturing process and later both are removed; 0030-0036 and figures 4-7.
It would have been obvious to one of ordinary skill in the art at the time of the invention to remove the seed layer as taught by Savastlouk in order to prevent an electrical connection between vias.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure; see PTO 892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS J GAMINO whose telephone number is (571)270-5826. The examiner can normally be reached M-F 9-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Keith Walker can be reached at 5712723458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CARLOS J GAMINO/Examiner, Art Unit 1735
/KEITH WALKER/Supervisory Patent Examiner, Art Unit 1735
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