DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li et al. (US 20240204109 A1; Li).
Regarding claim 17, Li discloses a semiconductor device comprising: a first transistor over a substrate (carrier wafer not shown; ¶39), comprising:
a first semiconductor channel layer (Fig. 5F, 412; ¶33); first source/drain (Fig.5F, 420; ¶36) epitaxy structures on opposite ends of the first semiconductor channel layer; and a first gate structure (Fig. 5F,424;¶37) wrapping around the first semiconductor channel layer; an isolation layer (Fig. 5F,418; ¶35) over the first gate structure; and a second transistor above the first transistor, comprising: a second semiconductor channel layer (Fig.5F,408; ¶33); second source/drain epitaxy structures (Fig.5F, 446;¶42) on opposite ends of the second semiconductor channel layer; and a second gate structure (Fig.5F, 450; ¶43) over the isolation layer and wrapping around the second semiconductor channel layer, wherein a width of the second gate structure is different from a width of the first gate structure. (Clear from cited figures)
The carrier wafer is removed after the completed device is formed. Therefore, the claimed structure is formed over a substrate as claimed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20240204109 A1; Li).
Regarding claim 18, Li discloses a semiconductor device of claim 17, but is silent on wherein a bottom surface of the isolation layer has a width different from a width of a top surface of the isolation layer.
This is simply a change in the shape of a structure that would not change the mode of operation of the device. Therefore, before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to change the shape of the isolation layer because where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Regarding claim 20, Li discloses a semiconductor device of claim 17, wherein one or both of the first gate structure and the second gate structure has a tapered profile.
This is simply a change in the shape of a structure that would not change the mode of operation of the device. Therefore, before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to change the shape of the isolation layer because where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04 IV A
Allowable Subject Matter
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The relevant art (US 20240204109 A1) discloses forming a first semiconductor stack , a sacrificial layer, and a second semiconductor stack in a stacked structure; etching a fist stack to a first width, replacing the sacrificial layer with a spacer layer; flipping the stacked structure to etch the second semiconductor stack to a second width; and forming stacked all around gate structures of different widths. The art is silent on the limitations cited below in combination with the rest of the claimed limitations.
Regarding claim 19, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " a plurality of isolation structures between the first and second source/drain epitaxy structures, wherein each of the isolation structures has a tapered sidewall.”, as recited in Claim 19, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 1-16 are allowed.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The relevant art (US 20240204109 A1) discloses forming a first semiconductor stack , a sacrificial layer, and a second semiconductor stack in a stacked structure; etching a fist stack to a first width, replacing the sacrificial layer with a spacer layer; flipping the stacked structure to etch the second semiconductor stack to a second width; and forming stacked all around gate structures of different widths. The art is silent on the limitations cited below in combination with the rest of the claimed limitations.
Regarding claim 1, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " etching the sacrificial layer such that a top width of the sacrificial layer is different from a bottom width of the sacrificial layer;”, as recited in Claim 1, with the remaining features.
Regarding claim 8, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " forming a source/drain recess extending through the first semiconductor stack, the sacrificial layer and the second semiconductor stack,”, as recited in Claim 8, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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