DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Domestic Benefit
No claim to an application for domestic benefit.
Foreign Priority
No claim to an application for foreign priority.
Information Disclosure Statement
No information disclosure currently provided.
Drawings
The drawings are objected to because of a minor typographical informality: Figures 2-14 depict a light gray dotted horizontal line that appears to indicate a doped region 104 of 100; this line is faint and difficult to see in the drawings.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following minor typographical informality:
Specification, paragraph 0002 states, “s memory device”, what is “s”?
Appropriate correction is required.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title or similar is suggested:
-- MEMORY DEVICE WITH DUAL WORK-FUNCTION BURIED WORD LINES AND ADJACENT FLUORINE-CONTAINING REGION AND MANUFACTURING METHOD THEREOF--.
Claim Objections
Claim 7 is objected to because of the following minor typographical informality: it is unclear if “comprises” should be “comprise” or “comprises”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 15, 16 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially level” recited in claims 2 and 18 is a relative term that renders the claim indefinite. The specification does not provide a standard for ascertaining the requisite degree of “levelness” and one of ordinary skill in the art would not be reasonable apprised of the scope of the invention. Specifically, it is unclear what range of vertical offset or misalignment between the bottom of the first fluorine-containing region and the top of the first word line layer would fall within, or outside of, the scope of “substantially level.” For purpose of examination on the merits, “level” is interpreted as requiring the surfaces to be at the same vertical position. However, the metes and bounds of the claim remain unclear due to the modified term “substantially.”
Claims 15 and 16 recite, “forming a barrier layer…between forming the cap layer” and “forming a barrier layer…between forming the second word line layer” respectively. The term “between” is ambiguous. It is unclear whether “between” refers to a temporal relationship (i.e., the barrier layer is formed after one step and before another) or a spatial relationship. Even assuming a temporal meaning, the claims fail to identify between which two specific steps the barrier layer is formed. The specification does not resolve this ambiguity. For purpose of examination , the term is interpreted as a temporal limitation. However, the metes and bounds of these claims remain unclear.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CN 114400180 A to Yan et al. (“Yan”).
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Regarding independent claim 1, Yan teaches of a memory device (see English translation of background section: “In dynamic random access memory (DRAM) devices”), comprising:
a substrate 10 (“substrate”; Figures 2a,2f, 2g, 5);
a first word line layer 221 (“first gate electrode”; Figures 2c, 2f, 3g, 5; English translation, “Similarly, the same type of leakage also occurs in the gate and drain regions of the Buried Word Line (BWL) structure. , and this vulnerability is an important parameter that affects the final performance and yield of DRAM products. At the same time, as the critical dimension (CD) of the buried word line becomes smaller and smaller, the resistance value of the metal word line becomes larger and larger, which affects the speed and performance of the MOS.” Therefore this is a word line) in (i.e., inside trench) the substrate 10;
a second word line layer 222 (“second gate electrode”; Figures 2d, 2f, 2g, 5; as per above explanation this is a word line layer) in (i.e., inside trench) the substrate 10 and over the first word line layer 221;
a gate dielectric layer 21 (“gate insulating layer”; Figures 2b, 2f, 2g, 5) lining (i.e., 21 lines 22) the first word line layer 22/221 and the second word line layer 22/222; and
source/drain regions (English translation makes clear that there are source/drain regions at the upper surface of 10 adjacent 22:
After the gate structure 20 is formed, the substrate 10 on both sides of the gate structure 20 is the active region of the semiconductor device, and ion implantation is performed on the active region to form a source region and a drain region.
The doping ions of the source region and the drain region may be N doping ions. N-doped ions refer to the ions doped with electronic properties, which may include at least one of phosphorus, arsenic and antimony.
In one embodiment, the energy and dose of fluorine ion implantation to the surface of the gate structure 20 are greater than the energy and dose of fluorine ion implantation to the surface of the substrate 10 to reduce the impact on the source and drain regions .
The substrates on both sides of the gate structure 20 are the active regions of the semiconductor device, and after ion implantation is performed on the active regions, source regions and drain regions are formed.
The first doped region 31 and the second doped region 32 are formed by fluorine ion implantation, wherein the energy and dose of the ion implantation to the surface of the gate structure 20 are greater than those of the ion implantation to the surface of the substrate 10 . energy and dose to reduce the effect on the source and drain regions.
) on the substrate 10 and on opposite sides of the second word line layer 22/222, wherein one of the source/drain regions (as explained supra) comprises a first fluorine-containing region 31 (“first doped region”; Figures 2e, 2f, 2g, 5; English translation: “By implanting fluorine ions on the upper surfaces of the substrate and the gate structure, and after annealing, a first doping region is formed at the junction of the substrate and the gate insulating layer, and the first doping region contains fluorine ions, and fluorine ions are formed in the first doping region. The bond energy is stronger, which can effectively reduce the leakage of GIDL, and at the same time, the annealing step can reduce the resistance value of the metal in the gate structure”) adjacent to the second word line layer 222.
Regarding claim 7, Yan teaches wherein a portion of one of the source/drain regions (i.e., as explained in claim 1 rejection supra) does not comprises fluorine (see Figure 5; only an edge portion of the source/drain region contains fluorine 31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3-4, 5, 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over CN 114400180 A to Yan et al. (“Yan”) in view of US 2016/0172488 A1 to Oh et al. (“Oh”).
Yan teaches all limitations of independent claim 1 from which claim 3 depends.
Regarding claim 3, Yan teaches in Figures 2g and 5 of etching back word line or gate electrode layer 22, in order to remove the negative influences of fluorine inside the gate electrode layer. Then Yan teaches of forming plugs and interconnects atop the substrate for capacitor and bit line connections.
Yan never expressly shows filling in the exposed surfaces of the etched back gate electrode layer 22.
The problem encountered by Yan as made clear by Oh in paragraph 0048 is that Yan’s word line/gate electrode layer is exposed.
Oh teaches in Figures 2A and 4E along with paragraph 0048 of using a caping layer 116 to cover the top gate electrode 115.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize that combining Oh’s protective layers to Yan’s invention would have been beneficial as best states by Oh’s paragraph 0048, “The capping layer 116 may serve to protect the gate electrode 107.”
Regarding claim 4, Oh in combination with Yan teaches a barrier layer (119 is a barrier layer in Oh’s Figure 4E that is between cap 116 and top word line/gate electrode 115. See Examiner’s Annotated Zoomed-In View Figure 4E of Oh, infra) between the cap layer (116 of Oh) and the second word line layer (115 of Oh).
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Yan teaches all limitations of independent claim 1 from which claim 5 depends.
Yan teaches all limitations of independent claim 1 from which claim 6 depends.
Yan teaches all limitations of independent claim 1 from which claim 8 depends.
Regarding claims 5, 6 and 8, Yan teaches in English translation that the word line/gate electrode 22 may be “two layers sequentially filled in the gate trench.” Further, the first lower gate electrode 221 may be titanium nitride while the second top gate electrode 222 may be tungsten thereby teaching that the work function is different between electrodes in a trench creating a dual work function buried word line.
The problem encountered by Yan as suggested by Oh is that the work function of each electrode may be diluted during reactions and methods of formation of the semiconductor device.
Oh remedies this issue as suggested in Figure 4E and paragraph 0090 in order to prevent unwanted dilution of the work function metals – the lower first gate electrode layer 111 is stacked with top second gate electrode layer 115 along with separating barrier layer 119 and also including other barrier/liner layers.
Therefore, in combination Yan and Oh teach that a portion of the gate dielectric (Oh in Figure 4E there is gate dielectric 106) layer above a top surface of the first word line layer (Oh in Figure 4E there is bottom first word line 111 that is below a top second word line 115) comprises fluorine (Yan teaches the benefits of including a fluorine source/drain region that is at the top sidewall of the buried word line trench).
Therefore, in combination Yan and Oh teach that a fluorine concentration (Yan’s Figure 2E does appear to teach of doping the gate dielectric layer 21, specifically number 32) of a portion of the gate dielectric layer (Oh in Figure 4E there is gate dielectric 106) lining the first word line layer (Oh in Figure 4E there is bottom first word line 111 that is below a top second word line 115) is lower (given that the main concentration of Fluorine in Yan is always at top of the trench, see 32 in Yan where 32 is inside 21) than a fluorine concentration of a portion of the gate dielectric layer lining the second word line layer (Oh in Figure 4E there is bottom first word line 111 that is below a top second word line 115 with gate dielectric 106).
Therefore, Oh teaches of a barrier layer (Oh’s Figure 4E number 119) between the first word line layer (Oh’s Figure 4E number 111) and the second word line layer (Oh’s Figure 4E number 115).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize that combining Oh’s protective layers and stacked gate structure to Yan’s invention would have been beneficial as best stated by Oh’s paragraph 0048, “The capping layer 116 may serve to protect the gate electrode 107.”; Oh’s paragraph 0090, in order to preserve the work function of the lower and upper gate by providing a stacked gate structure with barrier layers.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over CN 114400180 A to Yan et al. (“Yan”) in view of US 2022/0077155 A1 to Huang.
Yan teaches all limitations of independent claim 1 from which claim 9 depends.
Regarding claim 9, Yan does not expressly teach of an isolation region separating different regions.
The problem encountered by Yan as suggested by Huang’s Figures is that there is a lack of isolation between different regions of the semiconductor device.
Huang teaches throughout the Figures and in paragraph 0054 that the isolation region may be fluoride-doped silicate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize that combining Huang’s isolation region with Yan’s invention would have been beneficial in order to provide electrical isolation between regions while using a superior gap fill material like fluoride-doped silicate.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over CN 114400180 A to Yan et al. (“Yan”) in view of US 2012/0032257 A1 to Ananthan et al. (“Ananthan”).
Yan teaches all limitations of independent claim 1 from which claim 10 depends.
Regarding claim 10, Yan teaches of a first bottom word line/gate electrode 221 and a second top word line/gate electrode 222. Yan teaches that 221 is titanium nitride and 222 is tungsten therefore teaching of a buried dual work function word line.
The problem encountered by Yan as suggested by Ananthan is that the method of Yan is not simplified by using polysilicon for both top and bottom word line layers.
Ananthan fixes this problem teaching in Figure 4C and Figure 6 of a dual gate with low and high work functions respectively of 124 and 122. See paragraphs 0033-0034 of Ananthan both 122 and 124 may contain polysilicon but have different work functions.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize that combining Ananthan’s polysilicon dual work function gate electrodes with Yan’s invention would have been beneficial in order to reduce processing steps by using polysilicon for both gate electrode layers.
Allowable Subject Matter
Claim 2 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 2 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 2, wherein a bottom of the first fluorine-containing region is substantially level with a top of the first word line layer.
Independent claim 11 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 11, a manufacturing method of a memory device, comprising: forming a trench in a substrate; forming a gate dielectric layer lining the trench in the substrate; forming a first word line layer over the gate dielectric layer and in the trench; after forming the first word line layer, performing an implantation process to form a first fluorine-containing region in the substrate; and after the implantation process is complete, forming a second word line layer in the trench and over the first word line layer.
Dependent claims 12-20 contain allowable subject matter, because they depend on the allowable subject matter1 of claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as listed on the current Notice of References Cited-892 Form:
US 2004/0248364 A1 to Hsiao et al.: illustrates in Figure 2E of fluorine doping in a side wall of a trench to grow thicker oxide in Figure 2F. The trench is filled with a gate/ conductive layer 216 that is NOT a word line. The word line is 244 in Figure 2J. Therefore this is not a buried word line.
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18 June 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
1 Note that claims 15-16 and 18 are rejection under 35 USC 112(b) supra.
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