DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Domestic Benefit
Present application 18/602,163 filed 03/12/2024 claims priority from provisional application 63/589,046 filed 10/10/2023.
Foreign Priority
No claim to an application for foreign priority.
Information Disclosure Statements
The two information disclosure statements respectively submitted on 03/12/2024 and 04/24/2025 were file before first Office action. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the two information disclosure statements are considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5, 7-9, 17 and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0355733 A1 to Liang et al. (“Liang”).
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The applied reference has a common Applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding independent claim 1, Liang teaches of a method (as defined below), comprising:
forming a first dielectric layer 311A (“heat dissipation layer”; Figure 3D; paragraphs 0037,0029,0011,0011: 311 may be same material as 110 or 111 that in at least one embodiment may be dielectric) on a semiconductor structure (as defined below), the semiconductor structure (as defined herein) including a semiconductor device layer 122A (“semiconductor devices”; Figure 3A,3B; paragraphs 0014,0033) having a frontside (side closest to 311A) and a backside (side furthest to 311A), a first substrate 110T_1 (“carrier”; Figures 3B,3D; paragraph 0029) disposed on the backside (side furthest to 311A) of the semiconductor device layer 122A and a first interconnect structure 124A (“interconnect structure”; Figures 3B,3D; paragraph 0024) disposed on the frontside (side closest to 311A) of the semiconductor device layer 122A;
forming a plurality of first vias 332A (“vias”; Figure 3D; paragraph 0031) through the first dielectric layer 311A and extending to the first interconnect structure 124A, the first vias 332A having a first thermal conductive material (paragraph 0031,0021: 332 is same material as 132 that is in at least one embodiment aluminum) with a thermal conductivity greater than about 10 W/m·K (as stated in Drawings of present application’s provisional application: 237 W/m·K);
forming a second dielectric layer 311C (“heat dissipation layer”; Figure 3E; paragraph 0042) on a second substrate 122B (see Figure 3E);
forming a plurality of second vias 332B (see Figure 3E) through the second dielectric layer 311C and extending to the second substrate 112B, the second vias 311C having a second thermal conductive material (paragraph 0031,0021: 332 is same material as 132 that is in at least one embodiment aluminum) with a thermal conductivity greater than about 10 W/m·K (as stated in Drawings of present application’s provisional application: 237 W/m·K);
bonding (see Figure 3E) the second dielectric layer 311C to the first dielectric layer 311A and the second vias 332B to the first vias 332A; and
forming a second interconnect structure 124C/133/332C on the backside (side furthest to 311A) of the semiconductor device layer 122A.
Regarding claim 2, Liang teaches wherein the forming of the second interconnect structure 124C/133/332C includes thinning or removing (see Figure 3D to Figure 3E) the first substrate 110T_1.
Regarding claim 5, Liang teaches wherein the first and second thermal conductive materials 332 are electric conductive materials (see paragraphs 0031,0021: 332 is same material as 132 that is in at least one embodiment aluminum; “The through vias 132 are formed of conductive materials such as copper, aluminum, tungsten, alloy, a combination thereof, and/or the like”).
Regarding claim 7, Liang teaches wherein the first and second thermal conductive materials 332 have different material compositions (see paragraphs 0031,0021: 332 is same material as 132 that is in at least one embodiment aluminum; “The through vias 132 are formed of conductive materials such as copper, aluminum, tungsten, alloy, a combination thereof, and/or the like” Therefore, there may be at least one embodiment where the different 332s, 332A and 332B may be different materials).
Regarding claim 8, Liang teaches wherein the first and second dielectric layers 311A,311C are made of a dielectric material (as explained in claim 1 rejection supra) with a thermal conductivity greater than about 10 W/m·K (see paragraph 0011; 311A,311B may be the same material as 110 or 111 wherein 111 may be 500 W/m·K).
Regarding claim 9, Liang teaches wherein the first and second dielectric layers 311A,311C are made of a dielectric material (as explained in claim 1 rejection supra) with a thermal conductivity less than about 10 W/m·K (see paragraph 0010; 311A,311B may be the same material as 110 or 111 wherein 110 may be glass that is necessarily below 100 W/m·K).
Regarding independent claim 17, Liang teaches in Figure 3G of semiconductor device (refer to claim 1 rejection supra), comprising:
a semiconductor device layer 122A;
a frontside interconnect structure 124A over the semiconductor device layer 122A;
a backside interconnect structure 124C under the semiconductor device layer 122A; and
a substrate 122B bonded to the frontside interconnect structure 124A through a bonding structure (as defined below),
wherein the bonding structure (as herein defined) includes:
a dielectric layer 311A; and
a plurality of thermal pillars 332A extending through the dielectric layer 311A, the thermal pillars 332A having first ends interfacing the frontside interconnect structure 124A and second ends interfacing the substrate 122B.
Regarding claim 19, Liang teaches in Figure 3G wherein the bonding structure (without loss of anticipation of claim 1, the claimed bonding structure may be 311A+311C with 332A+ 332B) further includes:
a thermal sheet IF1 (see paragraph 0043: there may be an interface that may be metallic) dividing the dielectric layer 311A+311C into an upper portion 311C in thermal coupling with the substrate 122B and a lower portion 311A in thermal coupling with the frontside interconnect structure 124A.
Regarding claim 20, Liang teaches wherein the thermal pillars (without loss of anticipation of claim 1, the claimed thermal pillars may be 332A+ 332B) each has a sidewall having a first tapered portion and a second taper portion that is tapered in an opposite direction with respect to the first tapered portion (i.e., there is a reverse taper between 332A and 332B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3-4 are rejected under 35 U.S.C. 103 as being obvious over US 2024/0355733 A1 to Liang et al. (“Liang”).
The applied reference has a common Applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Liang teaches all limitations of claim 1 from which claim 3 depends.
Regarding claims 3 and 4, Liang teaches of a via hole formation between Figure 3C and Figure 3D, such that over filling and then planarization in order to arrive at a flat surface as illustrated in Figure 3D for bonding in Figure 3E would be required.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to recognize that given the preponderance of evidence (i.e., prior art of Liang’s Figures 3D-3E) it is more likely than not that the limitations of claims 3-4 are not patentable because of the flat surface provided for bonding between dielectric-to-dielectric and metal-to-metal surface bonding thereby forming the via holes, filling the via holes and planarizing is prima facie obvious.
Note of Amendments for Allowability
It is understood that Applicant may make a statement under 35 U.S.C. 102(b)(2)(C) to overcome the prior art rejections. However, Liang may easily be overcome because Liang’s vias are electrically conductive unlike present applications thermally conductive vias: A simple incorporation of claim 6 or a small phrase stating that no electrical signal passes through the thermal vias would overcome the prior art rejections.
Allowable Subject Matter
Claims 6, 10 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 6 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 6, wherein the first and second thermal conductive materials are electric non-conductive materials.
Claims 10 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 10, wherein the second vias are partially embedded in the second substrate.
Claims 18 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 18, wherein the thermal pillars are arranged in rows and columns in forming an array.
Claim 11 contains allowable subject matter, because the closest prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other elements of claim 11, a method, comprising: forming a first interconnect structure on a first side of a semiconductor device layer; forming a bonding structure connecting the first interconnect structure and a substrate, the bonding structure including a dielectric layer and an array of thermal conductive pillars extending through the dielectric layer, the thermal conductive pillars being electrically isolated from the semiconductor device layer; and forming a second interconnect structure on a second side of the semiconductor device layer, the second side of the semiconductor device layer facing away from the first side of the semiconductor device layer.
Regarding claim 11, the bolded part supra is not taught by the prior art of Liang.
Dependent claims 12-16 contain allowable subject matter, because they depend on the allowable subject matter of claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P DULKA whose telephone number is (571)270-7398. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ELISEO RAMOS-FELICIANO can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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23 June 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
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