DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 102 3
A. Claims 1, 2, and 6-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2005/0017363 (“Lin”). 3
III. Claim Rejections - 35 USC § 103 5
A. Claims 3-5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of US 2001/0029100 (“Huang”). 5
B. Claims 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over US 2007/0170486 (“Park”). 8
IV. Allowable Subject Matter 11
V. Response to Arguments 11
Conclusion 11
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 1, 2, and 6-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2005/0017363 (“Lin”).
With regard to claim 1, Lin discloses, generally in Figs. 3 and 6a,
1. (Currently Amended) An interconnect structure comprising:
[1] a first dielectric layer [220 or uppermost 510] over a substrate 210 [¶¶ 24-25, 35-36];
[2] a first metal layer [240 or uppermost 520] over the first dielectric layer [220 or uppermost 510] and having a first segment and a second segment separated from the first segment [by “opening 242” (¶ 27); opening in 520 shown but not labeled in the figures and discussed in ¶ 36];
[3] a metal via [340 or 630 (¶¶ 31, 39)] comprising a first portion between the first and second segments of the first metal layer [240 or uppermost 520], and a second portion above the first metal layer [240 or uppermost 520],
wherein
[4a] the metal via [340 or 630] extends into the first dielectric layer [220 or uppermost 510, respectively], and
[4b] a bottommost surface of the metal via [340 or 630] is above a bottom surface of the first dielectric layer [220 or uppermost 510, respectively]; and
[5] a second metal layer [330 or 620] over the metal via [340 or 630, respectively],
[6] wherein from a top view the second metal layer [330 or 620] comprises a metal line extending across the first and second segments of the first metal layer [240 or uppermost 520] [as show in Figs. 3 and 6a (see discussion below)],
[7] wherein from a cross-sectional view, the first portion of the metal via [340 or 630] has opposite sidewalls respectively offset from opposite sidewalls of the second portion of the metal via [340 or 630] [as shown in Figs. 3 and 6a].
With regard to feature [2] of claim 1, Lin states that “[c]onductive runners 240 may then be formed in or on the insulating layer 220” (Lin: ¶ 27; emphasis added), “a second layer of conductive runners 330 is formed in or on the insulating layer 310” (Lin: ¶ 30; emphasis added), and “a third layer of conductive runners 430 is formed in or on the insulating layer 410” (Lin: ¶ 34; emphasis added). Thus, the conductive runners, e.g., 240, 330, 520, are taken to be “on” the associated insulating layer.
With regard to feature [6] of claim 1, as drafted, the term “across” does not require the metal line to run entirely across each of the first and second segments of the first metal layer. The second metal layer 330 or 620 includes at least one metal line that extends partially across at least one, underlying, first and second metal segment of the first metal layer 240 or uppermost 510, as shown in Figs. 3 and 6a.
This is all of the limitations of claim 1.
With regard to claims 2 and 6-9, Lin further discloses,
2. (Original) The interconnect structure of claim 1, wherein a width between the opposite sidewalls of the second portion of the metal via [340 or 630] is greater than a width between the opposite sidewalls of the first portion of the metal via [340 or 630] [as shown in Fig. 6a].
6. (Original) The interconnect structure of claim 1, wherein the first metal layer 240 comprises aluminum, copper, tungsten, or cobalt [¶ 27].
7. (Original) The interconnect structure of claim 1, wherein the metal via 340 comprises aluminum, copper, tungsten, or cobalt [¶ 31].
8. (Original) The interconnect structure of claim 1, wherein the second metal layer 330 comprises aluminum, copper, tungsten, or cobalt [¶¶ 30, 27].
9. (Original) The interconnect structure of claim 1, wherein the second portion of the metal via [340 or 630] has a bottom surface in contact with a top surface of the first metal layer [240 or uppermost 520] [as shown in Figs. 3 and 6a].
III. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 3-5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of US 2001/0029100 (“Huang”).
Claims 3-5 and 10 read,
3. (Original) The interconnect structure of claim 1, wherein the metal via [340 or 630] further comprises a third portion below the first metal layer.
4. (Original) The interconnect structure of claim 3, wherein the third portion of the metal via has opposite sidewalls respectively offset from the opposite sidewalls of the first portion of the metal via.
5. (Original) The interconnect structure of claim 4, wherein a width between the opposite sidewalls of the third portion of the metal via is greater than a width between the opposite sidewalls of the first portion of the metal via.
10. (Original) The interconnect structure of claim 1, wherein
[1] the metal via further comprises a third portion below the first metal layer, and
[2] the third portion has a top surface in contact with bottom surfaces of the first and second segments of the first metal layer.
The prior art of Lin, as explained above, discloses each of the features of claim 1.
Lin does not show in Fig. 6a that there is a third portion of the via 340 or 630 below the first metal layer 240 or uppermost 520, but appears to suggests that there may be:
[0031] … As in the embodiment shown in FIG. 1, the conductive posts 340 may extend at least partially into the openings 242 in the underlying conductive runner 240. Although not illustrated, in some embodiments, conductive posts 340 may extend fully into the opening 242 and in yet other embodiments, the posts could extend at least partly through openings 242 and extend into underlying insulating layer 220.
(Lin: ¶ 31; emphasis added)
Lin states that the posts 340 “extend[ing] at least partly through openings 242 and extend[ing] into underlying insulating layer 220” is “not illustrated” (id.), but Fig. 1 does illustrate this.
Thus, it is not clear that Lin means by “the posts could extend at least partly through openings 242 and extend into underlying insulating layer 220” that “partly through” means “past the lower surface of the opening 242 in the runner 240.
Huang, like Lin, teaches a process of forming a strong metal via connection between metal layers 14, 50 by having the metal via 48 wrapping around the top, sidewall, and bottom of the lower metal layer 14 (Huang: Figs. 7 and 9; ¶¶ ). In this regards, Huang states,
[0033] Next, and referring to FIGS. 7 and 8, which show the continuation of the process after FIGS. 5 and 6, respectively, a conductive material 40 is deposited on the surface of the structure and into via 30 after photoresist 20 is removed. Such a material is preferably tungsten, but could be polysilicon, aluminum, titanium or any other conductive material suitable for making a contact. The conductive material 40 will to some extent fill the undercut 35 under areas 14a, 14b, 14c and 14d and will also come into contact with the edges of the first conductive layer 14 (where it is exposed within via 30) and areas 14a, 14b, 14c and 14d. FIGS. 7 and 8 show that the conductive material 40 has completely filled the undercut 35, …
[0034] The end result is a highly reliable contact between the first and second conductive layers 14 and 50. The cross 16 ensures a mechanical/electrical contact between the plug 48 and the first conductive layer 14 that is much improved over standard contacts in which these two structures meet at a strictly planar interface.
(Huang: ¶¶ 33-34; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to perform the undercut etch of Huang when forming the openings in the dielectric layers, e.g. 220 and 510, of Lin in which the metal vias are formed, such that the metal vias 340 and 630 extend past the bottom surface of the underlying metal layer 240 and uppermost 520 respectively, i.e. the claimed “first metal layer”, such that the metal vias 340 and 630 wrap around the top, sidewall, and bottom edges of the first and second metal segments of the first metal line 240 and uppermost 520, in order to provide a “much improved” “mechanical/electrical contact” between the overlying metal line and the first metal layer 240 and uppermost 520, as taught in Huang (¶¶ 33-34, supra).
This is all of the limitations of claims 3-5 and 10.
B. Claims 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over US 2007/0170486 (“Park”).
With regard to claim 11, Park discloses, generally in Figs. 2, 7, 8, and 13,
11. (Currently Amended) An interconnect structure comprising:
[1] a first dielectric layer [63 in Figs. 2, 7, and 8 (¶ 25); 99 in Fig. 13 (¶ 36)] over a substrate [51 in Figs. 2, 7, and 8 (¶ 23); 81 in Fig. 13 (¶ 34)];
[2] first [65 in Figs. 2, 7, and 8 (¶¶ 26, 28); 104 in Fig. 13 (¶¶ 37, 41)] and second [69 in Figs. 2, 7, and 8 (¶¶ 26, 28); 114 in Fig. 13 (¶¶ 37, 41)] metal structures above the first dielectric layer [63, 99, respectively];
[3] a metal via [78 in Fig. 8 (¶ 57); 123 in Fig. 13 (¶ 46)] extending from above the first [65, 104] and second [96, 114] metal structures to below the first [65, 104] and second [69, 114] metal structures through a slotted region [shown in Figs. 2, 7, and 8] between the first [65, 104] and second [69, 114] metal structures,
[4a] the metal via [78, 123] having
[4b] a first portion in the slotted region between the first [65, 104] and second [69, 114] metal structures and
[4c] a second portion below the first [65, 104] and second [69, 114] metal structures,
[4d] the first portion of the metal via [78 in Figs. 2, 7, and 8] having opposite sidewalls respectively offset from opposite sidewalls of the second portion of the metal via [because the sidewall of 78 at each of the first 65 and second 69 metal structure is set inwardly of the sidewalls of 78 below the first 65 and second 69 metal structures],
wherein
[5a] the second portion of the metal via [78, 123] extends into the first dielectric layer [63, 81], and
[5b] a bottommost surface of the second portion of the metal via [78, 123] is above a bottom surface of the first dielectric layer [63, 81]; and
[6] a metal line [127 in Fig. 13 (¶ 45)] extending across the metal via [123], the first metal structure [104], and the second metal structure [114].
The embodiment shown in Figs. 2 and 8 and the embodiment shown in Fig. 13 includes first dummy metal structure, 65 and 104, respectively, and second dummy metal structures, 69 and 114, respectively.
With regard to feature [6] of claim 11, the embodiment in Figs. 2 and 8 does not include the metal line 127 that is shown in the embodiment in Fig. 13.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a metal line configurated as shown in Fig. 13 in the embodiment in the embodiment shown in Figs. 2 and 8 in order to electrically connect the metal line 55 to an overlying metal line, e.g. like metal line 127, using the self-aligned contact 78, self-aligned by the dummy metal structures 65, 69, as taught in the discussion of the embodiment shown in Fig. 13:
[0046] Consequently, the first interconnection 127 may be electrically connected to the bit line 97 by the first contact plug 123 that sequentially penetrates the third, second, and first interlayer dielectric layers 115, 105, and 99. The first contact plug 123 is disposed between the first and second dummy patterns 104 and 114. …
(Park: ¶ 46)
This is all of the limitations of claim 11.
In the alternative, with regard to feature [4d] of claim 11, the embodiment shown in Fig. 13 does not show “the first portion of the metal via 123 having opposite sidewalls respectively offset from opposite sidewalls of the second portion of the metal via 123”, as required by feature [4d], because the embodiment shown in Fig. 13 does not include the undercutting/over-etching process shown in Fig. 7 (Park: ¶ 56).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to perform the undercutting/over-etching process shown in Fig. 7 in the embodiment shown in Figs. 12 and 13 that widens the opening 118 and exposes the lower surfaces of each of the first 104 and second 114 dummy metal patterns, in order to increase the cross-sectional area of the metal via 123 and the contact interface between 123 and each of the metal line 127 and the bit line 97, which would reduce both the resistivity of the metal via 123 and the contact resistance at the interfaces of the metal via with each of the metal line 127 and the bit line 97. As such, the embodiment shown in Figs. 2, 7, and 8 may be seen as an improvement to the embodiment shown in Fig. 13, in this aspect. (See MPEP 2143.)
This is all of the limitations of claim 11.
With regard to claims 12-16, the combination of the embodiments of Park, as explained under claim 11, above, further teaches,
12. (Original) The interconnect structure of claim 11, wherein a width between the opposite sidewalls of the first portion of the metal via 78 is less than a width between the opposite sidewalls of the second portion of the metal via 78 [as shown in Figs. 7 and 8].
13. (Original) The interconnect structure of claim 11, wherein the second portion of the metal via 78 forms a horizontal interface with a bottom surface of the first metal structure 65 [as shown in Figs. 7 and 8].
14. (Original) The interconnect structure of claim 13, wherein the second portion of the metal via 78 forms a horizontal interface with a bottom surface of the second metal structure 69 [as shown in Figs. 7 and 8].
15. (Original) The interconnect structure of claim 11, wherein the metal via 78 wraps three sides of the first metal structure 65 [as shown in Figs. 7 and 8].
16. (Original) The interconnect structure of claim 11, wherein the metal via 78 wraps three sides of the second metal structure 69 [as shown in Figs. 7 and 8].
IV. Allowable Subject Matter
Claims 17 and 20-22 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not reasonably teach or suggest—in the context of the claim17—the newly added limitation “wherein … a bottommost surface of the metal via is above a bottom surface of the first dielectric layer”.
V. Response to Arguments
Applicant’s arguments filed 08/20/2026 have been fully considered but they are
Applicant’s arguments with respect to claim(s) 1-16 have been considered but are moot because the new grounds of rejection do not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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