DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Claim Rejections - 35 USC § 102 3
A. Claims 17, 20, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2007/0170486 (“Park”). 4
IV. Claim Rejections - 35 USC § 103 6
A. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Park. 6
B. Claims 1-3 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 5,760,429 (“Yano”). 7
C. Claims 4, 5, and 10-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yano in view of US 2010/0013107 (“Sandhu”). 10
Conclusion 13
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s election without traverse of species group IV, the cancelation of claims 18 and 19 drawn to non-elected species groups, and the addition of new claims 21 and 22, either generic or directed to the elected species in the reply filed on 05/06/2026 is acknowledged.
III. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 17, 20, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2007/0170486 (“Park”).
With regard to claim 17, Park discloses, generally in Figs. 2 and 8,
17. (Original) An interconnect structure comprising:
[1] a first metal structure 69 [¶ 28] over a first dielectric layer 71 [¶ 29];
[2a] a metal via 78 [¶ 31] comprising
[2b] a first portion level with the first metal structure 69 and
[2c] a second portion above the first metal structure 69,
[2d] the first portion of the metal via 78 having a sidewall interfacing a sidewall of the first metal structure 69,
[2e] the second portion of the metal via 78 having a bottom surface interfacing a top surface of the first metal structure 69; and
[3a] a second metal structure 55(57) [¶ 31] over the metal via 78,
[3b] wherein from a top view the second metal structure 55(57) comprises a linear pattern having longitudinal sides respectively set back from opposite sides of the first metal structure 69 [as shown in Fig. 2, infra].
Fig. 8 of Park is reproduced below and oriented upside down and annotated to show claimed features [1] through [3a]. The third example in Fig. 2 is reproduced below and annotated to show claimed feature [3b].
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621
641
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(Annotated Fig. 8 of Park)
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209
712
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(Annotated 3rd example in Fig. 2 of Park)
This is all of the limitations of claim 17.
With regard to claims 20 and 22, Park further discloses,
20. (Original) The interconnect structure of claim 17, wherein
[1] the metal via 78 further comprises a third portion below the first metal structure 69, and
[2] the third portion has a top surface interfacing a bottom surface of the first metal structure 69 [as shown in Fig. 8].
22. (New) The interconnect structure of claim 17, wherein the first portion of the metal via 78 is narrower than the second portion of the metal via 78.
IV. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Park.
Claim 21 reads,
21. (New) The interconnect structure of claim 17, further comprising:
[1] a third metal structure level with the first metal structure and
[2] spaced apart from the first metal structure at least by the first portion of the metal via.
The prior art of Park, as explained above, teaches each of the features of claim 17.
While Fig. 8 of Park shows a third metal structure 65 (supra), Fig. 8 does not show that the first 69 and third 65 metal structures are “level”, i.e. at the same height.
Fig. 13 of Park shows a metal via 123 [¶ 46] having essentially the same configuration as shown in Fig. 8, including contacting first and third metal structures 104, 114 [¶ 46], and second metal structure 97 [¶ 46] contacting the top of the via (again viewed upside down, as with annotated Fig. 8 above). Fig. 13 of Park further shows that the first and third metal structures, 104 and 114, are “level”, i.e. at the same height, albeit not exactly “level”, in that a plane parallel to the top surface of the substrate 81 [¶ 42] can be drawn that extends through both the first and third metal structures, 104, 114. However, the claim as drafted does not require that the first and third metal structures be exactly level at all parts.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the first 69 and third 65 metal structures in Fig. 8 of Park to be “level”, i.e. at the same height, such as shown in Fig. 13, because Park shows that such a configuration of the first and third metal structure, 104 and 114, would be encountered in an actual device, such as that shown in Fig. 13.
This is all of the limitations of claim 21.
B. Claims 1-3 and 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 5,760,429 (“Yano”).
With regard to claim 1, Yano discloses, generally in Figs. 1(g),
1. (Original) An interconnect structure comprising:
[1] a first dielectric layer 22 over a substrate 1 [col. 11, lines 34, 42-43];
[2] a first metal layer [right of two 42B in Fig. 1(g); col. 11, lines 38-40] over the first dielectric layer 22 and having a first segment [right of two segments of right 42B] and a second segment [left of two segments of right 42B] separated from the first segment [Figs. 1(e) and 2 show that the hole 50 bisects the right one of the two metal layers 42B into two separated segments; col. 12, lines 53-59];
[3] a metal via 51 comprising a first portion between the first and second segments of the first metal layer [right 42B], and a second portion above the first metal layer [right 42B] [as shown in Fig. 1(g); col. 12, line 63-67]; and
[4] a second metal layer 43B over the metal via 51,
[5] wherein from a top view the second metal layer 43B [col. 11, lines 40-42] comprises a metal line extending across the first [right of two segments of right 42B] and second [left of two segments of right 42B] segments of the first metal layer [right 42B] [as shown in Fig. 1(g) and noting the Figs. 3 and 8(b) show the 43B is a line],
[6] wherein from a cross-sectional view, the first portion of the metal via [i.e. the portion of 51 between the first and second segments of the right 42B in Fig. 1(g)] has opposite sidewalls respectively offset from opposite sidewalls of the second portion [i.e. the portion of 51 above the right 42B] of the metal via 51 [as shown in Fig. 3; see explanation below].
With regard to feature [6] of claim 1, although the embodiment shown in Fig. 1(g) does not show the sidewalls of the first and second portions of the metal via 51 offset from each other, this is shown in Fig. 3, which is a cross section of Fig. 1(g) (col. 10, lines 58-61). For example, “reference number (2)” in Figs. 2-3 (col. 13, lines 32-67) shows that the portion of the metal via 51 above the metal segments of 42B (i.e. the claimed “second portion” of 51) is wider than the portion between the metal segments of 42B (i.e. the claimed “first portion” of 51), thereby giving the offset sidewalls of the first and second portions.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to make the metal via 51 extending through and connecting the right and left segments of the right hand 42B in Fig. 1(g) to have the structure of the metal via 51 shown as reference (2) in Figs. 2 and 3 because Yano states that Fig. 3 reference (2) shows a configuration of the via 51 in Fig. 1(g), i.e. “FIG. 3 is a cross-sectional perspective view showing one of the above manufacturing steps of the semiconductor device in accordance with the first embodiment of the present invention, corresponding to the step of FIG. 1(g)” (col. 10, lines 58-61; emphasis added).
This is all of the limitations of claim 1.
With regard to claims 2, 3, and 6-9,
2. (Original) The interconnect structure of claim 1, wherein a width between the opposite sidewalls of the second portion of the metal via 51 [i.e. portion of 51 above 42B] is greater than a width between the opposite sidewalls of the first portion of the metal via 51 [i.e. the portion of 51 between segments of 42B] [as shown in Fig. 3 and as just explained above].
3. (Original) The interconnect structure of claim 1, wherein the metal via 51 further comprises a third portion below the first metal layer [right 42B] [as shown in Figs. 1(g) and 3].
6. (Original) The interconnect structure of claim 1, wherein the first metal layer comprises aluminum, copper, tungsten, or cobalt [“the second-layer metal film 42A is formed on the first inter-layer insulating film 22 by successively depositing Ti, TiN, aluminum alloy containing several % of Si and Cu, and TiN with thicknesses of several tens nm, 100 nm, 800 nm, and 100 nm, respectively.” (col.12, lines 21-27) ].
7. (Original) The interconnect structure of claim 1, wherein the metal via 51 comprises aluminum, copper, tungsten, or cobalt [col. 12, lines 63-67; col. 13, lines 53].
8. (Original) The interconnect structure of claim 1, wherein the second metal layer comprises aluminum, copper, tungsten, or cobalt [“the third-layer metal film 43A is formed on the second inter-layer insulating film 23 by successively depositing Ti, TiN, aluminum alloy containing several % of Si and Cu, and TiN with thicknesses of several tens nm, 100 nm, 800 nm, and 100 nm, respectively.” (col. 13, lines 1-5)].
9. (Original) The interconnect structure of claim 1, wherein the second portion [i.e. the portion of 51 above 42B] of the metal via 51 has a bottom surface in contact with a top surface of the first metal layer [right 42B] [as shown in Fig. 3, as explained under claim 1].
C. Claims 4, 5, and 10-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yano in view of US 2010/0013107 (“Sandhu”).
Claims 4, 5, and 10 read,
4. (Original) The interconnect structure of claim 3, wherein the third portion of the metal via has opposite sidewalls respectively offset from the opposite sidewalls of the first portion of the metal via.
5. (Original) The interconnect structure of claim 4, wherein a width between the opposite sidewalls of the third portion of the metal via is greater than a width between the opposite sidewalls of the first portion of the metal via.
10. (Original) The interconnect structure of claim 1, wherein
[1] the metal via further comprises a third portion below the first metal layer, and
[2] the third portion has a top surface in contact with bottom surfaces of the first and second segments of the first metal layer.
The prior art of Yano, as explained above, teaches each of the features of claims 1 and 3.
Yano does not state that the sidewalls of the portion of the metal via 51 below the metal layer 42B, i.e. the claimed “third portion” are offset by being wider than the portion of the metal via 51 between the metal segments of the right hand one of 42B in Fig. 1(g).
Sandhu, like Yano, teaches a metal via, i.e. the righthand 120 (“the aperture 155 may be filled with a conductive material such as W, Cu, Al, Pd, Co, Ru, Ni, Pt, etc”; Sandhu: ¶ 26) extending between or through and connecting the metal lines 115 (“the conductive traces 115 may comprise a conductive metal material such as W, Cu, WSix,”; Sandhu: ¶ 19) in several metal levels (Sandhu: Figs. 2 and 6). Also like Yano, Sandhu teaches that the portions of the metal via 120 above the metal lines 115 are wider than the portion within the metal line 115. In addition, Sandhu teaches that the portions of the metal via 120 below the metal lines 115 are wider than the portion within the metal line 115. The benefit of the configuration shown in Fig. 6 is to increase the surface area of contact between the metal via 120 and the metal line 115 (¶¶ 28-29).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the claimed “third portion” of the metal via 51 of Yano below the metal segments of the righthand 42B in Fig. 1(g) to be wider than the portion between said metal segments, in order to increase the surface area of contact between the metal via 51 and the metal line segments, as taught in Sandhu, thereby increasing the conductivity of the contact between 51 and 42B. As such, Sandhu may be seen as an improvement to Yano in this aspect. (See MPEP 2143.)
So modified, all of the limitations of claims 4, 5, and 10 are met.
Claim 11 reads,
11. (Original) An interconnect structure comprising:
[1] a first dielectric layer over a substrate;
[2] first and second metal structures above the first dielectric layer;
[3] a metal via extending from above the first and second metal structures to below the first and second metal structures through a slotted region between the first and second metal structures,
[4a] the metal via having
[4b] a first portion in the slotted region between the first and second metal structures and
[4c] a second portion below the first and second metal structures,
[4d] the first portion of the metal via having opposite sidewalls respectively offset from opposite sidewalls of the second portion of the metal via; and
[5] a metal line extending across the metal via, the first metal structure, and the second metal structure.
With regard to claim 11, Yano discloses, generally in Fig. 1(g),
11. (Original) An interconnect structure comprising:
[1] a first dielectric layer 22 over a substrate 1;
[2] first [right of righthand 42B in Fig. 1(g)] and second [left of righthand 42B in Fig. 1(g)] metal structures above the first dielectric layer 22;
[3] a metal via 51 extending from above the first [right of righthand 42B] and second [left of righthand 42B] metal structures to below the first and second metal structures through a slotted region 50 between the first and second metal structures,
[4a] the metal via 51 having
[4b] a first portion in the slotted region 50 between the first [right of righthand 42B] and second [left of righthand 42B] metal structures and
[4c] a second portion below the first [right of righthand 42B] and second [left of righthand 42B] metal structures,
[4d]… [not taught] …
[5] a metal line 43B extending across the metal via 51, the first metal structure [right of righthand 42B], and the second metal structure [left of righthand 42B] [as shown in Fig. 1(g)].
With regard to feature [4d] of claim 11,
[4d] the first portion of the metal via 51 [i.e. between left and right segments of 42B] having opposite sidewalls respectively offset from opposite sidewalls of the second portion of the metal via [i.e. below the left and right segments of 42B]; and
As explained under claims 4, 5, and 10, Yano does not disclose this limitation. However, it is obvious in view of Sandhu for the reasons explained above, which apply equally here.
This is all of the limitations of claim 11.
With regard to claims 12-16, Yano modified according to Sandhu as explained under claims 4, 5, 10, and 11, above, further teaches,
12. (Original) The interconnect structure of claim 11, wherein a width between the opposite sidewalls of the first portion [between left and right segments of 42B] of the metal via 51 is less than a width between the opposite sidewalls of the second portion of the metal via 51 [below left and right segments of 42B] [as explained under claims 4, 5, and 10, above].
13. (Original) The interconnect structure of claim 11, wherein the second portion of the metal via 51 [below left and right segments of 42B] forms a horizontal interface with a bottom surface of the first metal structure [right of righthand 42B in Fig. 1(g)] [as explained under claims 4, 5, and 10, above].
14. (Original) The interconnect structure of claim 13, wherein the second portion of the metal via [below left and right segments of 42B] forms a horizontal interface with a bottom surface of the second metal structure [left of righthand 42B in Fig. 1(g)].
15. (Original) The interconnect structure of claim 11, wherein the metal via wraps three sides of the first metal structure [as shown in Fig. 6 of Sandhu].
16. (Original) The interconnect structure of claim 11, wherein the metal via wraps three sides of the second metal structure [as shown in Fig. 6 of Sandhu].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814
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