DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 7/2/2026 "Reply" elects without traverse and identifies claims 1-3, 5-6, 8-11, 13-14, 16, and 21-28 as being drawn to Invention I, Species A1. The Reply cancels claims 4, 7, 12, 15, and 17-20.
The 5/5/2026 restriction requirement is proper, is maintained, and is hereby made final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8, 10, 16, 21-22, and 24-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng (US Pub. No. 2020/0294866).
Regarding claim 1, in FIGs. 1-10, Cheng discloses a method, comprising: forming a first stack of alternating first semiconductor layers (108 within stack 104, paragraph [0046]) and second semiconductor layers (110 in stack 104, paragraph [0046]) over a substrate (102); forming a sacrificial semiconductor layer (108 over upper 112) over the first stack; forming a second stack of alternating third semiconductor layers (108 in stack 106) and fourth semiconductor layers (110 in stack 106) over the sacrificial semiconductor layer, wherein one or more of the first semiconductor layers have a thickness different from a thickness of one or more of the third semiconductor layers (tp vs tn, paragraph [0046]); replacing the sacrificial semiconductor layer with an isolation structure (802, paragraph [0067]); replacing the first semiconductor layers with a first gate structure (804, paragraph [0069]); and replacing the third semiconductor layers (1002, paragraph [0071]) with a second gate structure.
Regarding claim 2, in FIGs. 1-10, Cheng discloses that a distance between the second semiconductor layers is different from a distance between the fourth semiconductor layers (see FIG. 7A; tp vs tn, paragraph [0046]).
Regarding claim 8, in FIGs. 1-10, Cheng discloses that laterally etching the first semiconductor layers and the third semiconductor layers; forming first inner spacers (402 in stack 104, paragraph [0058]) on opposite sides of the laterally etched first semiconductor layers; and forming second inner spacers (402 in stack 106, paragraph [0058]) on opposite sides of the laterally etched third semiconductor layers, wherein one or more of the first inner spacers have a width (measured in the vertical direction of FIG. 4B) different from a width of one or more of the second inner spacers.
Regarding claim 10, in FIGs. 1-10, Cheng discloses a method comprising: forming a multilayer stack over a substrate (102), the multilayer stack comprising a first stack (104), a sacrificial layer (108 on upper 112) over the first stack, and a second stack (106) over the first stack, wherein the first stack comprises first channel layers (110), the second stack comprises second channel layers (110), and a distance between the first channel layers is different from a distance between the second channel layers (tp vs tn, paragraph [0046]); etching source/drain recesses in the multilayer stack (paragraph [0057]); replacing the sacrificial layer with an isolation layer (802, paragraph [0067]); forming first epitaxial source/drain regions (502, paragraph [0060]) in lower portions of the source/drain recesses; forming isolation structures (602, paragraph [0062]) over the first epitaxial source/drain regions; forming second epitaxial source/drain regions (604, paragraph [0063]) over the isolation structures; forming a first gate structure (804, paragraph [0069]) wrapping around the first channel layers; and forming a second gate structure (1002, paragraph [0071]) wrapping around the second channel layers.
Regarding claim 16, in FIGs. 1-10, Cheng discloses that the first epitaxial source/drain regions are of a conductivity type different from a conductivity type of the second epitaxial source/drain regions (paragraphs [0060] and [0063]).
Regarding claim 21, in FIGs. 1-10, Cheng discloses a method comprising: forming a first transistor over a substrate, the first transistor comprising a plurality of first channel layers (110 within 104) arranged one above another, a first gate structure (804) wrapping around each of the plurality of first channel layers, and first source/drain regions (502) on opposite sides of the first gate structure; and forming a second transistor over the first transistor, the second transistor comprising a plurality of second channel layers (110 within 106) arranged one above another, a second gate structure (1002) wrapping around each of the plurality of second channel layers, and second source/drain regions (604) on opposite sides of the second gate structure, wherein a distance between the plurality of first channel layers is different from a distance between the plurality of second channel layer (tp vs tn, paragraph [0046]).
Regarding claim 22, in FIGs. 1-10, Cheng discloses forming a plurality of first inner spacers (402 within 104) alternating with the plurality of first channel layers prior to forming the first source/drain regions; and forming a plurality of second inner spacers (402 within 106) alternating with the plurality of second channel layers prior to forming the second source/drain regions, wherein one or more of the plurality of first inner spacers has a width different from a width of one or more of the plurality of second inner spacers (measured vertically in FIG. 4B).
Regarding claim 24, in FIGs. 1-10, Cheng discloses forming an isolation structure (602) over one of the first source/drain regions, wherein one of the second source/drain regions is formed over the isolation structure.
Regarding claim 25, in FIGs. 1-10, Cheng discloses that the plurality of first channel layers comprise silicon (paragraph [0046]).
Regarding claim 26, in FIGs. 1-10, Cheng discloses that the plurality of second channel layers comprise silicon (paragraph [0046]).
Regarding claim 27, in FIGs. 1-10, Cheng discloses that the first source/drain regions are epitaxial structures of a first conductivity type (paragraphs [0060] and [0063]).
Regarding claim 28, in FIGs. 1-10, Cheng discloses that the second source/drain regions are epitaxial structures of a second conductivity type different from the first conductivity type (paragraphs [0060] and [0063]).
Allowable Subject Matter
Claims 3, 5-6, 9, 11, 13-14, and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by a distance between the second semiconductor layers is greater than a distance between the fourth semiconductor layers.
Regarding claim 5, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by a number of the second semiconductor layers is different from a number of the fourth semiconductor layers.
Regarding claim 6, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by a number of the second semiconductor layers is greater than a number of the fourth semiconductor layers.
Regarding claim 9, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by the width of the one or more of the first inner spacers is greater than the width of the one or more of the second inner spacers.
Regarding claim 11, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by the distance between the first channel layers is greater than the distance between the second channel layers.
Regarding claim 13, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by a number of the first channel layers is different from a number of the second channel layers.
Regarding claim 14, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by a number of the first channel layers is greater than a number of the second channel layers.
Regarding claim 23, the prior art failed to disclose or reasonably suggest the claimed method particularly characterized by the width of the one or more of the plurality of first inner spacers is greater than the width of the one or more of the plurality of second inner spacers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891
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