DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner acknowledges that in the response filed 7/6/2026, applicant cancelled claims 12-20 and added claims 21-29.
Claims 1-11 and 21-29 are pending and presented for examination.
Election/Restrictions
Applicant’s election of Invention I and Species I in the reply filed on 7/6/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Examiner notes that applicant’s response filed 7/6/2026 failed to identify the claims directed to the elected species. Based upon the elected species figures (Species I, Figures 10-14C), claims 9, 10, 25, and 26 are withdrawn as being directed to non-elected species II or III.
Claims 9, 10, 25, and 26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/6/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 8, 11, 21-23, and 27-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Smith et al (US 2022/0416048 and Smith hereinafter).
As to claims 1, 2, 8, and 11: Smith discloses [claim 1] a method (Figs. 1-13; [0030]) comprising: forming a lower semiconductor region (Fig. 1; 101bC in 101a; [0035]); forming an upper semiconductor region (Fig. 1; 101bC in 101b; [0035]) overlapping the lower semiconductor region (101bc in 101a); forming a lower gate dielectric (Fig. 1; 101bG2 in 101a {the high-k dielectric in each region 101a, 101b, 101c, etc. can be identical}; [0036] and [0045]) and an upper gate dielectric (101bG2 in 101b; [0036] and [0045]) on the lower semiconductor region (101bC in 101a) and the upper semiconductor region (101bC in 101b), respectively; forming a lower gate electrode (Fig. 1; 101bM; [0040]) on the lower gate dielectric (101bG2 in 101a) and the upper gate dielectric (101bG2 in 101b); etching back the lower gate electrode (Fig. 2; 101bM is removed from 101b, 102b, 103b, and 104b; [0045]); forming a gate isolation layer (Fig. 7; 710; [0048]) on the lower gate electrode (101bM) that has been etched back; and forming an upper gate electrode (Fig. 10; 1010; [0052]) over the gate isolation layer (710), wherein the upper gate electrode (1010) is on the upper gate dielectric (101bC in 101b); [claim 2] further comprising patterning the gate isolation layer (Fig. 7; 710 can be formed over the entire surface and then patterned to remain only in the desired area; [0050]); [claim 8] further comprising: etching the lower gate electrode (Fig. 12; 101bM; [0054]) and the upper gate electrode (1010); and filling a dielectric region (Fig. 13; 1310; [0055]) in spaces (1210; [0054]-[0055]) left by the etched lower gate electrode (101bM) and the etched the upper gate electrode (1010); [claim 11] wherein the lower semiconductor region (Fig. 1; 101bC in 101a) comprises a first semiconductor nanostructure (nanowires/nanosheets; [0030] and [0035]), and the upper semiconductor region (101bC in 101b) comprises a second semiconductor nanostructure (nanowires/nanosheets; [0030] and [0035]), and the method further comprises: forming a first source/drain region (first lower source/drain regions adjoining 101bC in 101a; [0035]) joining to the first semiconductor nanostructure (101bC in 101a); and forming a second source/drain region (first upper source/drain regions adjoining 101bC in 101b; [0035]) joining to the second semiconductor nanostructure (101bC in 101b).
As to claims 21-23: Smith discloses [claim 21] a method (Figs. 1-13; [0030]) comprising: forming a lower transistor (Figs. 1 and 13; 101a; [0034]) comprising: a first semiconductor region (Fig. 1; 101bC in 101a; [0035]); a first gate dielectric (Fig. 1; 101bG2 in 101a; [0036]) on the first semiconductor region (101bC in 101a); and a lower gate electrode (Fig. 13; 101bM; [0040]) on the first gate dielectric (101bG2); and forming an upper transistor (Figs. 1 and 13; 101b; [0034]) comprising: a second semiconductor region (Fig. 1; 101bC in 101b; [0035]) overlapping the first semiconductor region (101bC in 101a); a second gate dielectric (Fig. 1; 101bG2 in 101b; [0036]) on the second semiconductor region (101bC in 101b); and an upper gate electrode (Fig. 13; 1010; [0052]) on the second gate dielectric (101bG2 in 101b); and forming a gate isolation layer (Fig. 13; 710; [0049]) overlying and contacting the lower gate electrode (101bM), wherein the gate isolation layer (710) is further underlying and contacting the upper gate electrode (1010); [claim 22] wherein the lower transistor (Fig. 1; 101a) and the upper transistor (101b) have opposite conductivity types (101a can be PMOS and 101b can be NMOS; [0034]); [claim 23] further comprising forming an isolation region (Fig. 13; 1310; [0055]) comprising a sidewall (left sidewall) contacting edges (right edges) of the lower gate electrode (101bM), the gate isolation layer (710), and the upper gate electrode (1010).
As to claims 27-29: Smith discloses [claim 27] a method (Figs. 1-13; [0030]) comprising: forming a first Complementary Field-Effect Transistor (CFET) structure (Fig. 13; 101; [0034] and [0055]) comprising: a first lower Field-Effect Transistor (FET) (Figs. 1 and 13; 101a; [0034]) comprising a first lower gate electrode (Fig. 13; 101bM; [0040]); a first upper FET (Figs. 1 and 13; 101b; [0034]) comprising a first upper gate electrode (Fig. 13; 1010; [0052]) overlapping the first lower gate electrode (101bM); and a first gate isolation layer (Fig. 13; 710 between 101a and 101b; [0049]) between and joining to the first lower gate electrode (101bM) and the first upper gate electrode (1010); forming a second CFET structure (Figs. 1 and 13; can comprise 102 or 103 depending on whether a gate isolation is desired; [0034] and [0055]) comprising: a second lower FET (Figs. 1 and 13; either 102a or 103a; [0034] and [0055]) comprising a second lower gate electrode (101bM; [0040]); and a second upper transistor (Figs. 1 and 13; either 102b or 103b; [0034] and [0055]) comprising a second upper gate electrode (1010; [0052]) overlapping the second lower gate electrode (101bM); and forming an isolation region (Fig. 13; 1310; [0055]) comprising: a first sidewall (left sidewall of 1310) contacting first edges (right sidewall) of the first lower gate electrode (Figs. 1 and 13; interpreted to be 101bM that extends over the topmost 101bC in 102a) and the first upper gate electrode (Figs. 1 and 13; interpreted to be 1010 that extends over the topmost 101bC in 102b); and a second sidewall (Figs. 1 and 13; claim doesn’t state that the first and second sidewalls are different sidewalls so Examiner interprets them to be the same sidewall, just different regions of that same sidewall, namely the left sidewall of 1310) contacting second edges (right sidewall if 102 and left sidewall if 103 is the second CFET) of the second lower gate electrode (101bM around 101bC in 102a or 101bM around 101bC in 103a) and the second upper gate electrode (1010 around 101bC in 102b or 1010 around 101bC in 103b); [claim 28] further comprising forming a second gate isolation layer (Fig. 13; second CFET is 102, 710 between 102a and 102b is the second gate isolation layer; [0049]) between and joining to the second lower gate electrode (101bM around 101bC in 102a) and the second upper gate electrode (1010 around 101bC in 102b); [claim 29] wherein the second lower gate electrode (Fig. 13; second CFET is 103, 101bM around 101bC in 103a) physically contacts the second upper gate electrode (1010 around 101bC in 103b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Jung et al (US 2023/0352408 and Jung hereinafter).
Smith discloses wherein the forming the gate isolation layer comprises: depositing a dielectric layer (layer 710 can be formed by a blanket deposition and then patterned; [0050]).
Smith fails to expressly disclose planarizing the dielectric layer; and etching back the dielectric layer, wherein a remaining portion of the dielectric layer forms the gate isolation layer.
Jung discloses in Figs. 6 and 7 the process of forming a dielectric in selective areas by first forming a dielectric layer 8L in Fig. 6 and [0041], planarizing the dielectric layer (Fig. 7; CMP can be performed on 8L; [0042]); and etching back the dielectric layer (Fig. 7; wet etching/etching back in addition to CMP can be performed on 8L; [0042]), wherein a remaining portion (Fig. 7; 8; [0042]) of the dielectric layer (8L) forms the gate isolation layer (8).
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), a particular known technique, in the instant case selectively providing a dielectric layer, which is formed around other nanosheet structures, through planarization and etching back as taught by Jung; if this leads to the anticipated success, in the instant case a layer that can be formed only in desired areas to provide isolation between adjacent gate electrodes as needed in Smith, it is likely the product not of innovation but of ordinary skill.
Allowable Subject Matter
Claims 4-7 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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