Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: GFEC2023001-US-NP
Filling Date: 03/13/24
Inventor: Cave et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-18 and 21-22 in the reply filed on 06/19/26 is acknowledged.
Claims 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-16, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Thomas et al (US 2019/0044045 A1, Thomas1 hereinafter).
Regarding claim 1, Thomas1 discloses a structure (Figure 2-3, abstract) comprising: a semiconductor layer comprising a semiconductor material 220 having a first isotope with a first concentration of atoms (Paras. 55-59), the first concentration of atoms in the semiconductor material less than a natural abundance (Abstract, Paras. 56, 18) of the first isotope.
Thomas1 does not explicitly disclose the first concentration of atoms in the semiconductor material greater than zero parts per million.
However, Thomas1 discloses dopant atom in the semiconductor layer 220, 203 (Paras. 18, 56-66, abstract). Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain the first concentration of atoms in the semiconductor material greater than zero parts per million for intended purposes.
Regarding claim 2, Thomas1 discloses the structure of claim 1 wherein the first isotope has a non-integer nuclear spin (Para. 18).
Regarding claim 3, Thomas1 discloses the structure of claim 1 wherein the semiconductor material is silicon, and the first isotope has mass number 29 (Paras. 56, 36, copper).
Regarding claim 4, Thomas1 discloses the structure of claim 1 wherein the semiconductor material is germanium, and the first isotope has mass number 73 (Paras. 56, 20, tantalum).
Regarding claim 5, Thomas1 does not explicitly disclose the structure of claim 1 wherein the semiconductor material has a second isotope with a second concentration of atoms that is less than a natural abundance of the second isotope and greater than zero parts per million (Paras. 18, 54).
However, Thomas1 discloses multiple isotopes (Paras. 18, 54).
Thomas1 teaches semiconductor materials containing multiple isotopically purified materials. Thomas1 expressly discloses semiconductor host material comprising isotopically purified silicon and isotopically purified germanium, including silicon-germanium grown from isotopically purified silicon and germanium precursors.
Thomas1 discloses to reduce multiple nuclear-spin-bearing isotopes rather than merely one isotope (Paras. 18, 54, 56).
Regarding claim 6, Thomas1 discloses the structure of claim 5 wherein the semiconductor material is silicon-germanium (Para. 56).
Regarding claim 7, Thomas1 discloses the structure of claim 6 wherein the first isotope has mass number 29 (Paras. 56, 36, copper), and the second isotope has mass number 73 (Paras. 56, 20, tantalum).
Regarding claim 8, Thomas1 discloses the structure of claim 5 wherein the first isotope has a non-integer nuclear spin, and the second isotope has a non-integer nuclear spin (Paras. 18, 56, Si and Ge).
Regarding claim 9, Thomas1 does not explicitly disclose the structure of claim 8 wherein the semiconductor material has a third isotope with a third concentration of atoms that is greater than a natural abundance of the third isotope, and the third isotope has nuclear spin of zero.
However, Thomas discloses different percentage of the Si isotopes (Paras. 18, 56).
Thomas1 expressly teaches that reducing isotopes having nonzero nuclear spin results in increased concentration of zero-spin isotopes. For silicon, Thomas1 discloses Si greater than 93 atomic-percent and examples exceeding 94, 95, 96, 97, 98 and 99 atomic-percent (Para. 56).
Since natural Si is approximately 92.2%, a concentration greater than 93% is greater than natural abundance (Para. 56).
Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain the semiconductor material has a third isotope with a third concentration of atoms that is greater than a natural abundance of the third isotope, and the third isotope has nuclear spin of zero for intended purposes.
Regarding claim 10, Thomas1 does not explicitly disclose the structure of claim 1 wherein the semiconductor material has a second isotope with a second concentration of atoms, the second concentration of atoms is greater than a natural abundance of the second isotope, and the second isotope has nuclear spin of zero.
Thomas1 expressly teaches the enrichment of Si above its natural abundance as a consequence of depletion of different percentage of Si (Paras. 18, 55, 56).
Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain the semiconductor material has a second isotope with a second concentration of atoms, the second concentration of atoms is greater than a natural abundance of the second isotope, and the second isotope has nuclear spin of zero for intended purposes.
Regarding claim 11, Thomas1 discloses the structure of claim 1 further comprising: a field-effect transistor having a channel region in the semiconductor layer 203 (Paras. 46, 47).
Regarding claim 12, Thomas1 discloses the structure of claim 1 further comprising: a qubit device (Abstract, Paras. 18. 56) having a channel region in the semiconductor layer 203.
Regarding claim 13, Thomas1 discloses the structure of claim 1 wherein the semiconductor material of the semiconductor layer is a single-crystal semiconductor material (Para. 16).
Regarding claim 14, Thomas1 discloses the structure of claim 1 further comprising: a buried insulator layer; and a semiconductor substrate, wherein the buried insulator layer is disposed between the semiconductor substrate and the semiconductor layer 202 (Para. 52).
Regarding claim 15, Thomas1 discloses the structure of claim 14 wherein the semiconductor layer has a thickness in a range from about 3 nanometers to about 8 nanometers 220 (Para. 79), and the semiconductor material of the semiconductor layer is a single-crystal semiconductor material (Para. 16).
Regarding claim 16, Thomas1 discloses a method (Figures 2-3) comprising: forming a first semiconductor layer 220 (Paras. 18, 54-56) comprising a semiconductor material 220 (Para. 56) having a first isotope with a first concentration of atoms, wherein the first concentration of atoms in the semiconductor material is less than a natural abundance of the first isotope (Abstract, Paras. 55-59).
Thomas1 does not explicitly disclose the first concentration of atoms in the semiconductor material is greater than zero parts per million.
However, Thomas1 discloses dopant atom in the semiconductor layer 220, 203 (Paras. 56-66). Therefore, it would have been obvious to one of the ordinary skills of the art before the effective filling date of the claimed invention to obtain the first concentration of atoms in the semiconductor material greater than zero parts per million for intended purposes.
Regarding claim 21, Thomas1 discloses the method of claim 16 further comprising: forming a qubit device having a channel in a first portion of the first semiconductor layer 203 (Paras. 46, 47).
Regarding claim 22, Thomas1 discloses the method of claim 21 further comprising: forming an active electronic device (Paras. 33, 38) or a passive electronic device in a second portion of the first semiconductor layer 220.
Allowable Subject Matter
Claims 17 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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