DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant's election with traverse of Group I (claims 1-17) in the reply filed on 02/19/2026 is acknowledged. The traversal is on the ground(s) that “Applicant respectfully notes that claims 18-20 are directed to a non-transitory computer readable medium that, when executed by a controller of a processing chamber, causes the processing chamber to form a semiconductor device by performing all of the same method steps of claim 1. Accordingly, a search of the method of claim 1 will result in the same art to evaluate claims 18-20. Thus, there is no search burden. The Restriction Requirement, therefore, should be withdrawn and claims 18-20 should be rejoined”.
This is not found persuasive because searching and examining both process (Group I) and apparatus claims (Group II) certainly create serious burden on the examiner. Further, the process as claimed can be practice by another and materially different apparatus such as using an apparatus without having a controller.
The requirement is still deemed proper and is therefore made FINAL.
3. Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 02/19/2029.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
7. Claims 1-3, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2023/0124597 A1) in view of Voronin (US 2020/0266070 A1).
Note:
As to claim 1, Takahashi discloses a method of forming a semiconductor device, the method comprising:
selectively oxidizing a superlattice structure formed on a top surface of a semiconductor substrate to form a plurality of silicon germanium oxide (SiGeO) layers, the superlattice structure comprising a plurality of first layers of a first material and a corresponding plurality of second layers of a second material alternatingly arranged in a plurality of stacked pairs, the plurality of silicon germanium oxide (SiGeO) layers forming selectively on the plurality of first layers (paragraph 0035-0045, Fig 3AFig 3B);
removing the silicon germanium oxide (SiGeO) layers from each of the plurality of first layers (Fig 3B-3C, paragraph 0046-0062).
As to claim 1, Takahashi fails to disclose laterally etching each of the plurality of second layers to form a plurality of recessed second layers. Voronin discloses laterally etching each of the plurality of second layers to form a plurality of recessed second layers (17) (Fig 1A-1C, Fig 2A-2C; paragraph 0025-0039, 0040-0044). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Takahashi in view of Voronin by laterally etching each of the plurality of second layers to form a plurality of recessed second layers because it enable selective etching of a less reactive material in the presence of a more reactive material (paragraph 0021).
As to claim 2, Takahashi discloses the first material comprises silicon germanium (SiGe) and the second material comprises silicon (Si) (paragraph 0015). Voronin also discloses the first material comprises silicon germanium (SiGe) and the second material comprises silicon (Si) (See paragraph 0037).
As to claim 3, Takahashi discloses the first material comprises silicon (Si) and the second material comprises silicon germanium (Fig 3A). Voronin also discloses the first material comprises silicon (Si) and the second material comprises silicon germanium (paragraph 0027, paragraph 0044).
As to claim 9, Takahashi discloses the semiconductor device is a gate-all around (GAA) device (See paragraph 0015).
8. Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2023/0124597 A1) in view of Voronin (US 2020/0266070 A1) as applied to claims 1-3 above, and further in view of Ching et al. (US 2017/0162695 A1).
As to claim 4, Takahashi and Voronin fail to disclose each of the plurality of the recessed second layers has a recessed amount in a range of 1 nm 4 nm. As to claim 5, Takahashi and Voronin fail to disclose the recess amount is 3 nm. However, Voronin clearly teaches each of the plurality of the recessed second layers has a recessed amount (See Fig 1B). Ching discloses each of the plurality of the recessed second layers has a recess amount in a range 1 nm to 10 nm including 2 nm to 7 nm (paragraph 0037, within applicant’s claimed range). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Takahashi and Voronin in view of Ching by having a recessed amount between 2 nm to 4 nm or 3 nm because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (See MPEP 2144.05(I)).
9. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2023/0124597 A1) in view of Voronin (US 2020/0266070 A1) as applied to claim 1 above, and further in view of Chiang (US 2020/0227534 A1).
As to claim 6, Takahashi and Voronin fail to disclose each of the plurality of the silicon germanium oxide (SiGeO) layers has a thickness in a range from 0.5 nm to 3 nm. However, Takahashi clearly discloses forming the plurality of the silicon germanium oxide (SiGeO) layers (See paragraph 0040-0042). Chiang discloses forming plurality of the silicon germanium oxide (SiGeO) layers has a thickness in a range from 0.5 nm to about 2 nm (paragraph 0125). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Takahashi and Voronin in view of Chiang by having each of the plurality of the silicon germanium oxide (SiGeO) layers has a thickness in a range from 0.5 nm to 2 nm because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (See MPEP 2144.05(I)).
10. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2023/0124597 A1) in view of Voronin (US 2020/0266070 A1) as applied to claim 1 above, and further in view of Loubet (US 2020/0273753 A1).
As to claim 7, Takahashi discloses selectively oxidizing the superlattice structure (paragraph 0035-0037). Takahashi and Voronin fail to disclose a temperature in range of from 400 °C to 900 °C during the oxidizing step. Loubet discloses selectively oxidizing the superlattice structure at a temperature in a range of 400 °C to 800 °C (paragraph 0027-0028). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Takahashi and Voronin in view of Loubet by having a temperature between 400 °C to 800 °C during the oxidizing step because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (See MPEP 2144.05(I)).
11. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2023/0124597 A1) in view of Voronin (US 2020/0266070 A1) as applied to claim 1 above, and further in view of Kuan et al. (US 2021/0273047 A1).
As to claim 8, Takahashi and Voronin fail to disclose wherein less than or equal to 1 nm of the plurality of first layers is removed when removing the silicon germanium oxide (SiGeO) layers. However, Takahashi clearly teaches to remove silicon germanium oxide layer. Kuan teaches to form insulating layer comprises silicon germanium oxide by oxidation, wherein the silicon germanium oxide layer having a thickness from 0.1 nm to 1 nm (paragraph 0073). Kuan further teaches to partly remove the insulation layer (30) which comprises silicon germanium oxide (See paragraph 0074). Therefore, Kuan teaches less than or equals 1 nm of silicon germanium oxide is removed. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Takahashi and Voronin in view of Kuan by having less than 1 nm of the plurality of first layers is removed when removing the silicon germanium oxide (SiGeO) layers because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (See MPEP 2144.05(I)).
12. Claims 10-13, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over More (US 2022/0052203 A1) in view of Takahashi (US 2023/0124597 A1).
As to claim 10, More discloses a method of forming a semiconductor device, the method comprising:
recessing a source/drain region within a semiconductor substrate to form a recessed source/drain region (402) (Fig 1 step 115, Fig 4, paragraph 0029);
epitaxially growing a silicon germanium (SiGe) layer (602) from a bottom of the recessed source/drain region (402) to fill a portion of the recessed source/drain region (Fig 1 step 125; paragraph 0034, 0036; Fig 5), ;
pre-cleaning the recessed source/drain region
epitaxially growing a source/drain layer (806 or 902) on the silicon germanium (SiGe) layer (Fig 1 step 135, or step 140 paragraph 0044-0047).
As to claim 10, More fails to disclose selectively oxidizing a superlattice structure formed on a top surface of the semiconductor substrate above the recessed source/drain region
As to claim 11, More discloses the source/drain region (402) between 20 nm to 50 nm, or between 30 nm to 40 nm and the recessed source drain region has a depth in arrange of 30 nm to 40 nm, or 33 nm to 37 nm (See paragraph 0029, 0035, i.e. thickness of layer 602 deposit into the recess 402).
As to claim 12, More discloses the first material (122) comprises silicon germanium and the second material (124) comprises silicon (paragraph 0024).
As to claim 13, More discloses the first material (122) comprises silicon (Si) and the second material (124) comprises silicon germanium (SiGe) (See paragraph 0024).
As to claim 16, More discloses the source/drain layer (806 or 902) comprises one or more of silicon, silicon germanium, or group III/V compound semiconductor (paragraph 0045-0047).
As to claim 17, More discloses the semiconductor device is a gate-all around 0018-0020).
13. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over More (US 2022/0052203 A1) in view of Takahashi (US 2023/0124597 A1) as applied to claim 10-14, 16-17 above, and further in view of Chiang (US 2020/0227534 A1).
As to claim 14, More and Takahashi fail to disclose each of the plurality of the silicon germanium oxide (SiGeO) layers has a thickness in a range from 0.5 nm to 3 nm. However, Takahashi clearly disclose forming the plurality of the silicon germanium oxide (SiGeO) layers (See paragraph 0040-0042). Chiang discloses forming plurality of the silicon germanium oxide (SiGeO) layers has a thickness in a range from 0.5 nm to about 2 nm (paragraph 0125). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify More and Takahashi in view of Chiang by having each of the plurality of the silicon germanium oxide (SiGeO) layers has a thickness in a range from 0.5 nm to 2 nm because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (See MPEP 2144.05(I)).
14. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over More (US 2022/0052203 A1) in view of Takahashi (US 2023/0124597 A1) as applied to claim 10-14, 16-17 above, and further in view of Loubet (US 2020/0273753 A1).
As to claim 15, Takahashi discloses selectively oxidizing the superlattice structure (paragraph 0035-0037). More and Takahashi fail to disclose a temperature in range of from 400 °C to 900 °C during the oxidizing step. Loubet discloses to discloses selectively oxidizing the superlattice structure at a temperature in a range of 400 °C to 800 °C (paragraph 0027-0028). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify More and Takahashi in view of Loubet by having a temperature between 400 °C to 800 °C during the oxidizing step because in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (See MPEP 2144.05(I)).
Conclusion
15. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH X TRAN whose telephone number is (571)272-1469. The examiner can normally be reached Monday-Friday.
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BINH X. TRAN
Examiner
Art Unit 1713
/BINH X TRAN/ Primary Examiner, Art Unit 1713
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