DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is responsive to applicant’s amendment filed on 08/17/2026. Claims 1, 4-11, 14-24 are pending. Claims 1, 4-6, 8, 10, 14 have been amended. Claims 2-3, 12-13 have been cancelled. Claims 18-20 are withdrawn. Claims 21-24 are new claims. The applicant’s amendment along with the remark were sufficient to overcome the examiner’s previous ground of rejection under 35 U.S.C 103 with respect to independent claims 1 and 10. Claim 10 is allowed. Claims 14-17, 23-24 are allowed because they depend on allowed claim 10. However, the applicant’s amendment raises new ground of rejection under 35 U.S.C 112(a) as discussed below with respect to claims 1, 4-9 and 21-22.
Response to Arguments
3. Regarding to previous ground of rejection under 35 U.S.C 103 with respect to claim 1, the applicants stated:
“Takahashi relates to selective etching of a silicon germanium layer with respect to a silicon layer in processing a substrate in which the silicon layer and the silicon germanium layer are alternately stacked one above another. (Takahashi at [0018]). Takahashi discloses that "in the selective etching of the SiGe layer according to the present embodiment, selectively forming an oxide film Ox on a surface layer of the exposed surface of the SiGe layer among the Si layer and the SiGe layer stacked on the wafer W [], and removing the oxide film Ox thus formed [] are performed." (Id. at [0020]). Takahashi also discloses, however, that "when the desired etching amount is obtained for the SiGe layer, the oxide film Ox that remains in the surface layer of the wafer W, more specifically, in the surface layers of the exposed surfaces of the Si layer and the SiGe layer is removed." (Id. at [0021]) (emphasis added). Further, regarding "the oxide film Ox", Takahashi discloses that a "e.g., SiO2 film" is formed, and that it is formed by a plasma oxidation process by which "0* is applied to the SiGe layer so that the surface layer of the exposed surface of the SiGe layer is oxidized to form the oxide film Ox (SiO2 film) on the surface layer of the exposed surface. In this case, O2 bonds to Si other than Ge in the oxidation of the SiGe layer. As a result, Ge is gasified (turned into, for example, Ge2F4 or GeOF2) to be scattered." (Id. at [0023], [0039]) (emphasis added). Thus, contrary to the assertions of the Office, Takahashi does not disclose, teach, or suggest forming SiGeO layers, nor forming them selectively on the sidewall surfaces of a plurality of first layers comprising silicon germanium (SiGe).
Additionally, the Office acknowledges that Takahashi does not disclose laterally etching the plurality of second layers to form a plurality of recessed second layers, and turns to Voronin as allegedly remedying this deficiency of Takahashi. (Office Action at p. 4).
Voronin relates to systems and methods for selective etching at an interface between materials. (Voronin at [0002]). Voronin is silent with respect to forming a silicon germanium oxide (SiGeO) layer. Voronin is also silent as to "each first layer of the plurality of first layers comprising a sidewall surface facing a source/drain region" according to claim 1, as amended. Therefore, Voronin does not disclose, teach, or suggest selectively oxidizing a superlattice structure to form a plurality of SiGeO layers selectively on the sidewall surfaces facing a source/drain region of a plurality of first layers comprising SiGe. Thus, Voronin does not remedy the deficiencies of Takahashi in this regard, and claim 1 is patentable over the combination of Takahashi and Voronin.
Furthermore, Claim 1 recites laterally etching the plurality of second layers comprising silicon (Si) without etching the plurality of first layers comprising SiGe. As established in the present application, in gate-all-around (GAA) transistors with a dielectric inner spacer, silicon (Si) channels can be etched with high selectivity relative to the dielectric inner spacer, where the dielectric inner spacer protects silicon germanium (SiGe) layers in the superlattice structure. (Specification at [0006]). In cases where a dielectric inner spacer is not present, however, there is a need for processes in order to protect from SiGe recess during the Si channel recess. (Id.) The claimed invention provides a method of forming a device by advantageously protecting the SiGe layers during uniform and controllable Si channel lateral recess. (Id. at [0043], [0073]).
Takahashi not only fails to protect SiGe layers, but explicitly "performs a selective etching of a silicon germanium layer with respect to a silicon layer", which is the opposite of what is claimed in amended claim 1. (Takahashi at [0018]) (emphasis added). Further, the Office seeks to modify Takahashi with Voronin, which, contrary to Takahashi, teaches that "[a] possible advantage of embodiment methods described herein is to also enable so-called 'selectivity inversion' where the Si layers are selectively etched relative to exposed SiGe layers". (Voronin at [0021]) (emphasis added).
The mere fact that a reference may be modified in the manner suggested does not make the modification obvious unless the prior art suggested the desirability of the modification. In re Fritch, 972 F.2d 1260, 1266 (Fed. Cir. 1992) (citing In re Gordon, 733 F.2d 900, 902 (Fed. Cir. 1984)) (emphasis added). If a proposed modification would render the prior art invention being modified unsatisfactory for its intended purpose, there may be no suggestion or motivation to make the proposed modification. Gordon, 733 F.2d at 902.
The Office has not articulated any reasoning with rational underpinning as to why the person of ordinary skill in art would have used Voronin, which is solely concerned with methods of selectively etching Si over SiGe, to modify Takahashi, which is solely concerned with methods of selectively etching SiGe over Si. (See Voronin at [0021], Takahashi at [0018]). Combining Takahashi and Voronin in the manner suggested by the Office would render Takahashi inoperable for its intended purpose. Thus, Applicant respectfully submits that the Office has not met its burden of establishing a prima facie case of obviousness. For this further reason, the claimed invention is patentable over the combination of Takahashi and Voronin. Withdrawal of this basis of rejection is respectfully requested.”
The applicant’s amendment along with the remark were sufficient to overcome the examiner’s previous ground of rejection under 35 U.S.C 103 with respect to claim 1. However, upon further consideration, new ground of rejection under 35 U.S.C 112(a) were set forth as discussed below with respect to claims 1, 4-9, 21-22. Specifically, the examiner is unable to find proper support for the new limitation “lateral etching the plurality of second layers to form a plurality of recessed second layers without etching the plurality of first layers” (emphasis added) as recited in amended claim 1. The examiner clearly recognizes that applicants have support for “lateral etching the plurality of second layers to form a plurality of recessed second layers”. However, the applicants do not have proper support for new negative limitation “without etching the plurality of first layers”. On the contrary, in paragraph [0068], the applicants wrote “The plurality of second layers 106 may be laterally etched using any known etchant that is selective to the plurality of second layers 106, where the etchant etches the plurality of second layers 106 at a significantly higher rate than the plurality of first layers 104.” It is clear from the record that the plurality first layers are etched at a significantly lower rate with respect to the plurality of the second layers during lateral etching the plurality of second layers to form a plurality of recessed second layers. Claims 4-9, 21-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ) because they directly or indirectly depend on rejected claim 1.
Regarding to previous ground of rejection under 35 U.S.C 103 with respect to claim 10, the applicants stated:
“The Office Action acknowledges that More fails to disclose selectively oxidizing a superlattice structure formed on a top surface of the semiconductor substrate above the recessed source/drain region to form a plurality of SiGeO layers, the plurality of SiGeO layers forming selectively on the plurality of first layers, and admits that More further fails to disclose pre-cleaning the recessed source/region to remove the plurality of SiGeO layers. (Office Action at 8-9). The Office Action alleges that Takahashi remedies this deficiency. (Id. at p. 9-10).
As discussed above with respect to the rejection of claim 1, Takahashi does not disclose, teach, or suggest forming a plurality of SiGeO layers selectively on the sidewall surfaces of a plurality of first layers comprising SiGe, and does not disclose, teach, or suggest pre-cleaning the recessed source/drain region to remove the plurality of SiGeO layers and expose the sidewall surfaces of the plurality of first layers, according to claim 10 as amended. Thus, Takahashi does not remedy the deficiencies of More in this regard, and claim 10 is patentable over the combination of More and Takahashi.
Applicant respectfully requests reconsideration and withdrawal of this basis of rejection.”
The applicant’s amendment along with the remark were sufficient to overcome the examiner’s previous ground of rejection under 35 U.S.C 103 with respect to claim 10. Claim 10 is allowed. Claims 11, 14-17, 23-24 are allowed because they directly or indirectly depend on allowed claim 10.
Claim Rejections - 35 USC § 112
4. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
5. Claims 1, 4-9, 21-22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In line 11-12 of claim 1, the examiner is unable to find proper support for the new limitation “lateral etching the plurality of second layers to form a plurality of recessed second layers without etching the plurality of first layers” (emphasis added). The examiner considers “without etching the plurality of first layers” is a negative limitation. The examiner is unable to find proper support for the new negative limitation “without etching the plurality of first layers”. On the contrary, in paragraph [0068] of the Specification, the applicants wrote:
”[0068] For example, where the superlattice structure 103 is composed of a plurality of
second layers 106 comprising silicon (Si) and a plurality of first layers 104 comprising
silicon germanium (SiGe), the plurality of second layers 106 are laterally etched to form
the plurality of recessed second layers 106'. The plurality of second layers 106 may be
laterally etched using any known etchant that is selective to the plurality of second layers 106, where the etchant etches the plurality of second layers 106 at a significantly higher rate than the plurality of first layers 104. In some embodiments, a selective dry etch or wet etch process may be used. In one or more embodiments, the dry etch process includes exposing the plurality of second layers 106 to common gases for etching the silicon, reactive ion etching (RIE) with a remote plasma source, ammonia (NH₃), nitrogen trifluoride (NF₃), and hydrogen (H₂). In some embodiments, the plurality of second layers 106 may be etched using a wet etchant such as, but not limited to aqueous carboxylic acid/nitric acid/HF solution and aqueous citric acid/nitric acid/HF solution.” (emphasis added).
It is clear from the record that the first layer (104) is etched during the step of lateral etching the plurality of second layer because in paragraph [0068] the applicant wrote “The plurality of second layers 106 may be laterally etched using any known etchant that is selective to the plurality of second layers 106, where the etchant etches the plurality of second layers 106 at a significantly higher rate than the plurality of first layers 104.” Applicants do not have proper support for the limitation “lateral etching the plurality of second layers to form a plurality of recessed second layers without etching the plurality of first layers”.
Claims 4-9, 21-22 22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph because they directly or indirectly depend on rejected claim 1.
Allowable Subject Matter
6. Claims 10-11, 14-17, 23-24 are allowed.
7. The following is a statement of reasons for the indication of allowable subject matter:
As to claims 10-11, 14-17, 23-24, the cited prior arts fail to disclose or suggest selectively oxidizing a superlattice structure formed on a top surface of the semiconductor substrate above the recessed source/drain region to form a plurality of silicon germanium oxide (SiGeO) layers, the superlattice structure comprising a plurality of first layers comprising silicon germanium (SiGe) and a corresponding plurality of second layers comprising silicon (Si) alternatingly arranged in a plurality of stacked pairs, each first layer of the plurality of first layers comprising a sidewall surface facing the recessed source/drain region, the plurality of silicon germanium oxide (SiGeO) layers forming selectively on the sidewall surfaces of the plurality of first layers;
epitaxially growing a silicon germanium (SiGe) layer from a bottom of the recessed source/drain region to fill a portion of the recessed source/drain region;
pre-cleaning the recessed source/drain region to remove the plurality of silicon germanium oxide (SiGeO) layers.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shen et al. (US 2015/0099368 A1) discloses etching each of SiGe layers selectively relative each of Si layer.
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BINH X. TRAN
Examiner
Art Unit 1713
/BINH X TRAN/Primary Examiner, Art Unit 1713
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