DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/06/2026 (“04/06/2026 Submission”) has been entered.
In response to a final Office action mailed on 10/06/2025 (“10/06/2025 FOA”), the Applicant have amended independent claims 2, 7 and 12 in the 04/06/2026 Submission. The amendments to the independent claims 2, 7 and 12 substantively changed the scope of claims 2, 7 and 12 as well as the scope of their respective dependent claims.
Claims 1, 5, 8 and 10 are cancelled.
Currently, claims 2-4, 6-7, 9 and 11-13 are examined as below.
Response to Arguments
Applicant’s amendments to independent claims 2, 7 and 12 have overcome the prior-art rejections as set forth under line item number 3 in the 10/06/2025 FOA. However, previously-cited prior arts Kang and Akimoto still read on parts of the claims.
New reference is introduced. New grounds of rejections under 35 U.S.C. 103 are provided as follows.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 12/22/2025. The IDS has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Semiconductor Device with Improved Subthreshold Swing, On/Off Ratio, and Reliability
(Clean Version) Semiconductor Device with Improved Subthreshold Swing, On/Off Ratio, and Reliability
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-4, 6-7, 9 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2008/0203387 A1 to Kang et al. (“Kang”) in view of US 2007/0072439 A1 to Akimoto et al. (“Akimoto”), and further in view of US 2004/0097024 A1 to Doi.
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Regarding independent claim 2, Kang in Fig. 26 teaches a semiconductor device (Fig. 26 & ¶ 105, top gate type TFT) comprising:
an oxide semiconductor layer 48 (¶ 58, channel layer 48 is an oxide semiconductor layer);
a first conductive layer 50, 54 (Fig. 26, ¶ 57-¶ 58, a collective of source 50 and first metal oxide layer 54) overlapping with a first region (Fig. 26, left region) of the oxide semiconductor layer 48;
a second conductive layer 52, 56 (Fig. 26, ¶ 57-¶ 58, a collective of drain 52 and second metal oxide layer 56) overlapping with a second region (Fig. 26, right region) of the oxide semiconductor layer 48; and
a first insulating layer 46 (Fig. 26, ¶ 58, gate insulating layer 46) over the oxide semiconductor layer 48, the first conductive layer 50, 54, and the second conductive layer 52, 56,
wherein the oxide semiconductor layer 48 comprises a third region (Fig. 26, center region) between the first region (i.e., left region) and the second region (i.e., right region),
wherein the oxide semiconductor layer 48 comprises indium, gallium, and zinc (¶ 58),
wherein each of the first conductive layer 50, 54 and the second conductive layer 52, 56 has a layered structure (Fig. 26) including at least a first layer 54, 56 (Fig. 26, ¶ 58, first metal oxide layer 54, second metal oxide layer 56) and a second layer 50, 52 (Fig. 26, ¶ 57, source 50, drain 50) over and in contact with the first layer 54, 56 (Fig. 26),
wherein the first layer 54, 56 comprises a conductive metal oxide layer 54, 56 (¶ 58, first metal oxide layer 54, second metal oxide layer 56),
wherein the second layer 50, 52 comprises at least one of chromium, copper, tantalum, titanium, molybdenum, and tungsten (¶ 57, Cu).
However, Kang does not explicitly disclose wherein the oxide semiconductor layer has a crystalline structure.
Akimoto recognizes a need for increasing mobility of the transistor channel (¶ 6). Akimoto satisfies the need by providing a oxide semiconductor layer 409 (Figs. 5A-5C, ¶ 114, oxide semiconductor film 409) having a crystalline structure (¶ 109, oxide semiconductor film having crystallinity).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use the oxide semiconductor layer having a crystalline structure taught by Akimoto for the oxide semiconductor layer taught by Kang, so as to increase mobility of the transistor channel (Akimoto: ¶ 6).
However, the combination of Kang and Akimoto does not explicitly disclose wherein a side surface of the second layer of the first conductive layer comprises a first oxide region, wherein a side surface of the second layer of the second conductive layer comprises a second oxide region, and wherein the first insulating layer is in contact with the first oxide region, the second oxide region, and the third region of the oxide semiconductor layer.
Doi recognizes a need for preventing corrosion of metal films of a transistor (¶ 4, ¶ 54, ¶ 56). Doi satisfies the need by providing a side surface of a second layer 72 (Figs. 1D-1E, ¶ 43, ¶ 45, ¶ 52, core metal layer 72 is formed from core metal film 92 comprising copper) of a first conductive layer 7 (Fig. 1E, ¶ 52, source electrode 7) comprises a first oxide region 73c (Fig. 1E, ¶ 53, side protective layer 73c is formed by oxidizing core metal layer 72. That is, the side protective layer 73c is an oxide layer),
a side surface of a second layer 82 (Figs. 1D-1E, ¶ 43, ¶ 45, ¶ 52, core metal layer 82 is formed from core metal film 92 comprising copper) of a second conductive layer 8 (Fig. 1E, ¶ 52, drain electrode 8) comprises a second oxide region 83c (Fig. 1E, ¶ 53, side protective layer 83c is formed by oxidizing core metal layer 82. That is, the side protective layer 83c is an oxide layer).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the second layers taught by Kang and Akimoto with the first and second oxide regions taught by Doi, so as to prevent corrosion of metal films of a transistor (Doi: ¶ 4, ¶ 54, ¶ 56).
The combination of Kang, Akimoto and Doi would thus teaches the first insulating layer 46 (Kang: Fig. 26) in contact with the first oxide region 73c (Doi: Fig. 1E; Kang: Fig. 26, the layer 46 would be in contact with the side surface of the layer 50 including the oxide region 73c of Doi), the second oxide region 83c (Doi: Fig. 1E; Kang: Fig. 26, the layer 46 would be in contact with the side surface of the layer 52 including the oxide region 83c of Doi), and the third region of the oxide semiconductor layer (Kang: Fig. 26, center region of the layer 48).
Regarding claim 3, Kang in Fig. 26 teaches the conductive metal oxide layer 54, 56.
However, Kang does not explicitly disclose the conductive metal oxide layer comprises indium and zinc.
Akimoto recognizes a need for providing a material having a light transmitting property and reducing a contact resistance between the oxide semiconductor channel layer and a source/drain electrode (¶ 114, ¶ 116). Akimoto satisfies the need by providing a conductive metal oxide layer 411 (Figs. 5A-5C, ¶ 116, first conductive film 411) comprising indium and zinc (¶ 116).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use a material comprising indium and zinc taught by Akimoto for the metal oxide first layer taught by Kang, so as to provide a material having a light transmitting property and reducing a contact resistance between the oxide semiconductor channel layer and a source/drain electrode (Akimoto: ¶ 114, ¶ 116).
Regarding claim 4, Kang in Fig. 26 further teaches the second layer 50, 52 comprises copper (¶ 57, Cu).
Regarding claim 6, Kang in Fig. 26 further teaches the first insulating layer 46 comprises silicon oxide (¶ 58).
Regarding independent claim 7, Kang in Fig. 26 teaches a semiconductor device (Fig. 26 & ¶ 105, top gate type TFT) comprising:
an oxide semiconductor layer 48 (¶ 58, channel layer 48 is an oxide semiconductor layer);
a first conductive layer 50, 54 (Fig. 26, ¶ 57-¶ 58, a collective of source 50 and first metal oxide layer 54) overlapping with a first region (Fig. 26, left region) of the oxide semiconductor layer 48;
a second conductive layer 52, 56 (Fig. 26, ¶ 57-¶ 58, a collective of drain 52 and second metal oxide layer 56) overlapping with a second region (Fig. 26, right region) of the oxide semiconductor layer 48; and
a first insulating layer 46 (Fig. 26, ¶ 58, gate insulating layer 46) over the oxide semiconductor layer 48, the first conductive layer 50, 54, and the second conductive layer 52, 56,
wherein the oxide semiconductor layer 48 comprises a third region (Fig. 26, center region) between the first region (i.e., left region) and the second region (i.e., right region),
wherein the oxide semiconductor layer 48 comprises indium, gallium, and zinc (¶ 58),
wherein each of the first conductive layer 50, 54 and the second conductive layer 52, 56 has a layered structure (Fig. 26) including at least a first layer 54, 56 (Fig. 26, ¶ 58, first metal oxide layer 54, second metal oxide layer 56) and a second layer 50, 52 (Fig. 26, ¶ 57, source 50, drain 50) over and in contact with the first layer 54, 56 (Fig. 26),
wherein the first layer 54, 56 comprises a first element selected from the group consisting of chromium, copper, tantalum, titanium, molybdenum, and tungsten (¶ 58, Cr, Ti, Mo, W),
wherein the second layer 50, 52 comprises a second element selected from the group consisting of chromium, copper, tantalum, titanium, molybdenum, and tungsten (¶ 57, Cu),
wherein the first element is different from the second element (¶ 57-¶ 58),
wherein a side surface of the second layer 50 of the first conductive layer 50, 54 located over the first region (Fig. 26, left region) of the oxide semiconductor layer 48,
wherein a side surface of the second layer 52 of the second conductive layer 52, 56 located over the second region (Fig. 26, right region) of the oxide semiconductor layer 48.
However, Kang does not explicitly disclose wherein the oxide semiconductor layer has a crystalline structure.
Akimoto recognizes a need for increasing mobility of the transistor channel (¶ 6). Akimoto satisfies the need by providing a oxide semiconductor layer 409 (Figs. 5A-5C, ¶ 114, oxide semiconductor film 409) having a crystalline structure (¶ 109, oxide semiconductor film having crystallinity).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use the oxide semiconductor layer having a crystalline structure taught by Akimoto for the oxide semiconductor layer taught by Kang, so as to increase mobility of the transistor channel (Akimoto: ¶ 6).
The combination of Kang and Akimoto does not explicitly disclose a side surface of the second layer of the first conductive layer comprises a first oxide region, wherein a side surface of the second layer of the second conductive layer comprises a second oxide region, and wherein the first insulating layer is in contact with the first oxide region, the second oxide region, and the third region of the oxide semiconductor layer.
Doi recognizes a need for preventing corrosion of metal films of a transistor (¶ 4, ¶ 54, ¶ 56). Doi satisfies the need by providing a side surface of a second layer 72 (Figs. 1D-1E, ¶ 43, ¶ 45, ¶ 52, core metal layer 72 is formed from core metal film 92 comprising copper) of a first conductive layer 7 (Fig. 1E, ¶ 52, source electrode 7) comprises a first oxide region 73c (Fig. 1E, ¶ 53, side protective layer 73c is formed by oxidizing core metal layer 72. That is, the side protective layer 73c is an oxide layer),
a side surface of a second layer 82 (Figs. 1D-1E, ¶ 43, ¶ 45, ¶ 52, core metal layer 82 is formed from core metal film 92 comprising copper) of a second conductive layer 8 (Fig. 1E, ¶ 52, drain electrode 8) comprises a second oxide region 83c (Fig. 1E, ¶ 53, side protective layer 83c is formed by oxidizing core metal layer 82. That is, the side protective layer 83c is an oxide layer).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the second layers taught by Kang and Akimoto with the first and second oxide regions taught by Doi, so as to prevent corrosion of metal films of a transistor (Doi: ¶ 4, ¶ 54, ¶ 56).
The combination of Kang, Akimoto and Doi would thus teaches the first insulating layer 46 (Kang: Fig. 26) in contact with the first oxide region 73c (Doi: Fig. 1E; Kang: Fig. 26, the layer 46 would be in contact with the side surface of the layer 50 including the oxide region 73c of Doi), the second oxide region 83c (Doi: Fig. 1E; Kang: Fig. 26, the layer 46 would be in contact with the side surface of the layer 52 including the oxide region 83c of Doi), and the third region of the oxide semiconductor layer (Kang: Fig. 26, center region of the layer 48).
Regarding claim 9, Kang in Fig. 26 further teaches the second layer 50, 52 comprises copper (¶ 57, Cu).
Regarding claim 11, Kang in Fig. 26 further teaches the first insulating layer 46 comprises silicon oxide (¶ 58).
Regarding independent claim 12, Kang in Fig. 26 teaches a semiconductor device (Fig. 26 & ¶ 105, top gate type TFT) comprising:
an oxide semiconductor layer 48 (¶ 58, channel layer 48 is an oxide semiconductor layer);
a first conductive layer 50, 54 (Fig. 26, ¶ 57-¶ 58, a collective of source 50 and first metal oxide layer 54) overlapping with a first region (Fig. 26, left region) of the oxide semiconductor layer 48;
a second conductive layer 52, 56 (Fig. 26, ¶ 57-¶ 58, a collective of drain 52 and second metal oxide layer 56) overlapping with a second region (Fig. 26, right region) of the oxide semiconductor layer 48; and
a first insulating layer 46 (Fig. 26, ¶ 58, gate insulating layer 46) over the oxide semiconductor layer 48, the first conductive layer 50, 54, and the second conductive layer 52, 56,
wherein the oxide semiconductor layer 48 comprises a third region (Fig. 26, center region) between the first region (i.e., left region) and the second region (i.e., right region),
wherein the oxide semiconductor layer 48 comprises indium, gallium, and zinc (¶ 58),
wherein each of the first conductive layer 50, 54 and the second conductive layer 52, 56 has a layered structure (Fig. 26) including at least a first layer 54, 56 (Fig. 26, ¶ 58, first metal oxide layer 54, second metal oxide layer 56) and a second layer 50, 52 (Fig. 26, ¶ 57, source 50, drain 50) comprising copper (¶ 57, Cu) over and in contact with the first layer 54, 56 (Fig. 26).
However, Kang does not explicitly disclose wherein the oxide semiconductor layer has a crystalline structure, and
Akimoto recognizes a need for increasing mobility of the transistor channel (¶ 6). Akimoto satisfies the need by providing a oxide semiconductor layer 409 (Figs. 5A-5C, ¶ 114, oxide semiconductor film 409) having a crystalline structure (¶ 109, oxide semiconductor film having crystallinity).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use the oxide semiconductor layer having a crystalline structure taught by Akimoto for the oxide semiconductor layer taught by Kang, so as to increase mobility of the transistor channel (Akimoto: ¶ 6).
Kang does not explicitly disclose at least a first layer 54, 56 (Fig. 26, ¶ 58, first metal oxide layer 54, second metal oxide layer 56) comprising indium and zinc.
Akimoto recognizes a need for providing a material having a light transmitting property and reducing a contact resistance between the oxide semiconductor channel layer and a source/drain electrode (¶ 114, ¶ 116). Akimoto satisfies the need by providing at least a first layer 411 (Figs. 5A-5C, ¶ 116) comprising indium and zinc (¶ 116).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use a material comprising indium and zinc taught by Akimoto for the metal oxide first layer taught by Kang, so as to provide a material having a light transmitting property and reducing a contact resistance between the oxide semiconductor channel layer and a source/drain electrode (Akimoto: ¶ 114, ¶ 116).
Kang does not explicitly disclose wherein a side surface of the second layer of the first conductive layer comprises a first oxide region, wherein a side surface of the second layer of the second conductive layer comprises a second oxide region, and wherein the first insulating layer is in contact with the first oxide region, the second oxide region, and the third region of the oxide semiconductor layer.
Doi recognizes a need for preventing corrosion of metal films of a transistor (¶ 4, ¶ 54, ¶ 56). Doi satisfies the need by providing a side surface of a second layer 72 (Figs. 1D-1E, ¶ 43, ¶ 45, ¶ 52, core metal layer 72 is formed from core metal film 92 comprising copper) of a first conductive layer 7 (Fig. 1E, ¶ 52, source electrode 7) comprises a first oxide region 73c (Fig. 1E, ¶ 53, side protective layer 73c is formed by oxidizing core metal layer 72. That is, the side protective layer 73c is an oxide layer),
a side surface of a second layer 82 (Figs. 1D-1E, ¶ 43, ¶ 45, ¶ 52, core metal layer 82 is formed from core metal film 92 comprising copper) of a second conductive layer 8 (Fig. 1E, ¶ 52, drain electrode 8) comprises a second oxide region 83c (Fig. 1E, ¶ 53, side protective layer 83c is formed by oxidizing core metal layer 82. That is, the side protective layer 83c is an oxide layer).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the second layers taught by Kang and Akimoto with the first and second oxide regions taught by Doi, so as to prevent corrosion of metal films of a transistor (Doi: ¶ 4, ¶ 54, ¶ 56).
The combination of Kang, Akimoto and Doi would thus teaches the first insulating layer 46 (Kang: Fig. 26) in contact with the first oxide region 73c (Doi: Fig. 1E; Kang: Fig. 26, the layer 46 would be in contact with the side surface of the layer 50 including the oxide region 73c of Doi), the second oxide region 83c (Doi: Fig. 1E; Kang: Fig. 26, the layer 46 would be in contact with the side surface of the layer 52 including the oxide region 83c of Doi), and the third region of the oxide semiconductor layer (Kang: Fig. 26, center region of the layer 48).
Regarding claim 13, Kang in Fig. 26 further teaches the first insulating layer 46 comprises silicon oxide (¶ 58).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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