DETAILED ACTION
Allowable Subject Matter
Claim 27 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Claim 27 recites in part “wherein forming the active TSV and the dummy via further comprises: removing the second patterned photoresist after performing the second etch; forming a liner structure over the lower dielectric layer and within the active TSV opening and the dummy via opening; performing a further etch through bottom portions of the liner structure; forming a metal layer over the liner structure and within the active TSV opening and the dummy via opening after performing the further etch; and removing portions of the metal layer from over the liner structure to form the active TSV and the dummy via”.
To elaborate briefly on the above, while Tsai and Lin teach or suggest many of the limitations cited above, they do not teach or suggest the totality of the limitations of claim 27, thus resulting in an indication of allowable subject matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-26 & 28-35 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2016/0379963) by Tsai et al (“Tsai”) in view of (US-2019/0067157) by Lin et al (“Lin”).
Regarding claim 16, Tsai discloses in FIGs. 1-6 and related text, e.g., a method of forming a semiconductor device, the method comprising:
forming a lower dielectric layer (FIG. 2, 214) over a back-side surface (top) of a device substrate (202), wherein the device substrate has a front-side surface (bottom) that is opposite the back-side surface, and the device substrate has a peripheral region (away from center of 202) laterally separated from a device region (center of 202);
forming a wire (208f) over a front-side surface of the device substrate within the peripheral region;
performing one or more etches (par. 26; 212 are the result of such etches, by definition) through a top surface of the lower dielectric layer, wherein the one or more etches form a through substrate via (TSV) opening through the lower dielectric layer and the device substrate within the peripheral region (see FIG. 2; as far as “TSV”, it is the result shown in FIG. 4), wherein a bottom surface of the TSV opening is separated from the wire (see FIG. 2), and
forming a dielectric liner (216) within the TSV opening;
performing a second etch through the TSV opening that extends the TSV opening to a top surface of the wire (see FIG. 3); and
forming a metal layer (FIG. 4, 406) within the TSV opening wherein the metal layer forms a TSV within the TSV opening and a dummy via within the dummy via opening.
Tsai does not disclose “wherein the one or more etches form a dummy via opening extending into the lower dielectric layer within the device region, wherein a bottom surface of the dummy via opening is above the front- side surface of the device substrate”, “forming a dielectric liner within … the dummy via opening” and “forming a metal layer within … the dummy via opening”.
Lin discloses in FIG. 20 and related text, e.g., “wherein the one or more etches form a dummy via opening (FIG. 8A, 114) extending into the lower dielectric layer (see par. 44; such an approach is considered by Lin: “For example, the recesses 114 may be formed in the substrate 52 of the integrated circuit dies 50 such that the dummy TSVs 116 are surrounded by non-conductive materials on all sides except the top side (e.g., the side of the dummy TSVs 116 level with the back side of the substrate 52). The non-conductive materials may be insulating materials”) within the device region (center of the chip), wherein a bottom surface of the dummy via opening is above the front-side surface of the device substrate (as pointed out above, par. 44 of Lin suggests such an approach)”, “forming a dielectric liner (“insulating materials”; multiple layers are explicitly suggested; hence, a second layer after lower dielectric layer (such as a liner) is within the scope of Lin’s teachings) within … the dummy via opening” and “forming a metal layer (FIG. 9, 116) within … the dummy via opening”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of Tsai with “wherein the one or more etches form a dummy via opening extending into the lower dielectric layer within the device region, wherein a bottom surface of the dummy via opening is above the front- side surface of the device substrate”, “forming a dielectric liner within … the dummy via opening” and “forming a metal layer within … the dummy via opening” as taught by Lin, in order to allow for heat removal from underlying chip (par. 46) and, in order to simplify the processing steps of making device by making as many steps as possible at the same time (“through silicon vias” and “dummy vias” steps at the same time).
Regarding claim 17, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., further comprising: receiving an imaging chip (FIG. 1, 100) with one or more image sensors (“imaging chip” is not mentioned explicitly by Tsai, but par. 3 explicitly states that the function of chips can be very varied (‘and the like’); hence, “imaging chip” with “image sensors” is at the very least obvious in light of Tsai’s explicit teachings);
bonding the imaging chip to a device chip that comprises the lower dielectric layer, the device substrate, the wire, the TSV, and the dummy via (see FIG. 4);
receiving a logic chip (FIG. 5, 500) with one or more active devices; and
bonding the logic chip to the device chip (see FIG. 5).
Regarding claim 18, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., further comprising:
forming an inter-layer dielectric (ILD) layer (various parts of 204) between the device substrate and the wire;
performing the one or more etches that expose a top surface of the ILD layer (compare FIGs. 2 & 3; par. 32 explicitly states that it is done with “one or more etching processes”; hence, in an intermediate etch, some sort of top surface of ILD layer is exposed; hence, meeting limitations); and
performing an etch that extends the TSV opening through the ILD layer (final result shown in FIG. 3, after final etch).
Regarding claim 19, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., wherein forming the dielectric liner comprises:
forming a first dielectric liner along a top surface of the lower dielectric layer and through the TSV opening and the dummy via opening; and forming a second dielectric liner on an exposed surface of the first dielectric liner and inner sidewalls of the first dielectric liner within the TSV opening and the dummy via opening (see par. 30; a combination of multiple layers/materials is suggested by Tsai for layer 216).
Regarding claim 20, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., wherein an etch is performed through bottom surfaces of the dielectric liner within the peripheral region and the device region (see FIG. 3).
Regarding claim 21, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., wherein performing the one or more etches comprises:
forming a patterned photoresist on the lower dielectric layer (see pars. 26-28 use of “patterning process” and “photoresists” is discussed in detail as explicitly used, and as a suggested alternative for use; hence, “patterned photoresist” is at the very least obvious in light of Tsai’s explicit teachings), wherein the patterned photoresist has a TSV mask opening within the peripheral region and a dummy-via mask opening within the device region (by definition, in combination of Tsai and Lin; “TSV” is at the edge (peripheral) and “dummy via” is in center (device)), the TSV mask opening having a width greater than a width of the dummy-via mask opening (see center of FIG. 2; that is the “device region”; it has to fit 5 “dummy vias” shown by Lin; they are smaller width by definition); and
performing a first etch through the TSV mask opening and the dummy-via mask opening to concurrently form the TSV opening and the dummy via opening (see rejection of claim 1; it discusses “concurrency” in motivation to combine; such limitations are at the very least obvious in order to simplify the processing steps of making the device, in order to improve efficiency, etc.).
Regarding claim 22, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., substantially the entirety of claimed subject matter but do not explicitly state “further comprising forming a dielectric film on the back-side surface of the device substrate, and forming the lower dielectric layer on the dielectric film, wherein the one or more etches form the dummy via opening extending through the lower dielectric layer and into the dielectric film, and wherein the second etch is performed through the TSV opening and the dummy via opening to expose the wire within the peripheral region and the dielectric film within the device region”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Tsai and Lin with “further comprising forming a dielectric film on the back-side surface of the device substrate, and forming the lower dielectric layer on the dielectric film, wherein the one or more etches form the dummy via opening extending through the lower dielectric layer and into the dielectric film, and wherein the second etch is performed through the TSV opening and the dummy via opening to expose the wire within the peripheral region and the dielectric film within the device region”, since Tsai teaches explicitly teaches an ARC layer (par. 27; 214, the “lower dielectric film” of claim 16) and it is notoriously well-known that the ARC film can be a combination of layers instead, thus resulting in “dielectric film” and “lower dielectric film”, as required by the claim; also, Tsai explicitly teaches additional optional layers in par. 28 (optional hard mask layers); the combination of “optional hard mask” and “ARC layer” would also read on required two different “dielectric films”; “dummy via” limitations are all as suggested by Lin in par. 44, as was discussed in claim 16.
Regarding claim 23, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., further comprising forming a dielectric film on the back-side surface of the device substrate, and forming the lower dielectric layer on the dielectric film, wherein the one or more etches form the dummy via opening having a bottom surface disposed above a bottom surface of the lower dielectric layer, such that a portion of the lower dielectric layer separates the bottom surface of the dummy via opening from the dielectric film (“dummy via” limitations are all as suggested by Lin in par. 44, as was discussed in claim 16).
Regarding claim 24, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., further comprising: forming a plurality of dielectric layers over the front-side surface of the device substrate and forming an inter-layer dielectric (ILD) layer between the plurality of dielectric layers and the wire (as was discussed in claim 18; regarding plurality of layers, see the various metals 208c/d/e; there are separate dielectric layers above/below them; thus plurality of layers), wherein the first dielectric liner and the second dielectric liner are formed extending through the plurality of dielectric layers and terminate at a top surface of the ILD layer (all as discussed in claim 18), and wherein forming the metal layer forms the TSV with an upper portion laterally surrounded by the first dielectric liner and the second dielectric liner (by definition; those were the cited layers above) and a bottom portion extending through the ILD layer from the upper portion to the wire, outer sidewalls of the bottom portion directly contacting the ILD layer (if one considers 402 to be part of “metal layer” (402/406), then the limitations are met).
Regarding claim 25, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., a method of forming a semiconductor structure, the method comprising:
forming a dielectric layer on a back-side surface of a device substrate of a first semiconductor chip, wherein the device substrate comprises a peripheral region laterally offset from a device region (as was discussed above in claim 16; “dielectric layer” here, being “lower dielectric layer” in claim 16);
forming an active through substrate via (TSV) within the peripheral region, wherein the active TSV extends through the dielectric layer and the device substrate (as discussed in claim 16);
forming a dummy via within the dielectric layer over the device region (see claim 16), wherein a bottom surface of the dummy via is separated from the device substrate (see claim 16);
providing a second semiconductor chip comprising a device within the device region and a bond pad (FIG. 5, 108a reads on the bond pad in second chip) within the peripheral region (see claim 17; “imaging chip”; all the regions (device and peripheral) are same as in first chip); and
bonding the second semiconductor chip to the first semiconductor chip such that the active TSV is coupled to the bond pad (if one considers TSV to be 404 in FIG. 5 (instead of 406), then limitations are met) and the dummy via is aligned with the device (as discussed in claim 16).
Regarding claim 26, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., further comprising: forming a first patterned photoresist on the dielectric layer (see claim 21), wherein the first patterned photoresist has a TSV opening (see claim 21) within the peripheral region and covers the device region (by definition; whatever does not have an opening, is covered);
performing a first etch through the TSV opening to form an active TSV opening extending through the lower dielectric layer, and the device substrate (as discussed in claim 16);
removing the first patterned photoresist (happens between FIGs. 1 & 2);
forming a second patterned photoresist (FIG. 2, 218) over the dielectric layer and within the active TSV opening, wherein the second patterned photoresist is formed with a dummy via opening within the device region and performing a second etch through the dummy via opening to form a dummy via opening extending through the lower dielectric layer.
Tsai and Lin do not explicitly state “wherein the second patterned photoresist is formed with a dummy via opening within the device region and performing a second etch through the dummy via opening to form a dummy via opening extending through the lower dielectric layer”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Tsai and Lin with “wherein the second patterned photoresist is formed with a dummy via opening within the device region and performing a second etch through the dummy via opening to form a dummy via opening extending through the lower dielectric layer”, since Tsai’s TSV goes all the way through all the layers until the wire, and Lin’s TSV goes only through some of dielectric layers on top of substrate, therefore it would be obvious to have only a single etch for forming the dummy TSVs of Lin.
Regarding claim 28, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., wherein forming the active TSV and the dummy via comprises:
forming an active TSV opening through the dielectric layer and the device substrate (see claim 16);
forming a dummy via opening in the dielectric layer laterally offset from the active TSV opening (see claim 16);
forming a liner structure comprising one or more dielectric liners along a top surface of the dielectric layer, along sidewalls of the active TSV opening and the dummy via opening, and over bottom surfaces of the active TSV opening and the dummy via opening (see claim 16);
etching through bottom portions of the liner structure (see claim 16); and
forming a metal layer (402/406) directly on inner sidewalls of the liner structure and within the active TSV opening and the dummy via opening.
Regarding claim 29, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., wherein the etching through the bottom portions of the liner structure further recesses a top surface of the liner structure and reduces thicknesses of portions of the liner structure extending along sidewalls of the active TSV opening and the dummy via opening (by definition; when one etches an opening, all the exposed layers will suffer some erosion, no matter how small; these limitations are met by definition), thereby enlarging the active TSV opening and the dummy via opening before forming the metal layer (by definition).
Regarding claim 30, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., wherein forming the metal layer comprises: depositing the metal layer over the liner structure and within the active TSV opening and the dummy via opening after etching through the bottom portions of the liner structure (as discussed above); and
planarizing the metal layer to remove the metal layer from a top surface of the liner structure and form substantially coplanar top surfaces of the active TSV and the dummy via (see FIG. 4; all metals are shown to be flat; hence, “planarizing” and “coplanar”, in combined device).
Regarding claim 31, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., a method of forming a device, the method comprising:
providing a substrate (see claim 16);
forming a dielectric layer on the substrate (see claim 16);
forming a plurality of active TSV openings through the dielectric layer and the substrate within a peripheral region of the substrate (see claim 16; also, Tsai shows plurality);
forming a plurality of dummy via openings within the dielectric layer aligned over a device region of the substrate (see claim 16; also, Lin shows plurality), wherein the dummy via openings terminate above a surface of the substrate (see claim 16); and
forming a metal layer within the active TSV openings and the dummy via openings to form a plurality of active TSVs and a plurality of dummy vias, wherein the plurality of active TSVs surround an outer perimeter of the plurality of dummy vias (see claim 16; also, since active TSVs are on edges, they surround dummy TSVs by definition).
Regarding claim 32, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., further comprising bonding an imaging chip to a device chip comprising the substrate (see claim 17), wherein:
the imaging chip comprises an imaging device within the device region (see claim 17) and a bond pad (FIG. 4, 108a) within the peripheral region;
at least one of the active TSVs (404) is aligned with the bond pad;
at least one of the dummy vias is aligned with the imaging device (by definition; they are both in the center of respective devices; thus aligned); and the plurality of dummy vias are electrically isolated from active devices of the imaging chip (Lin teaches electrical isolation or electrical connection for dummy vias; so both are disclosed (pars. 42-44 of Lin).
Regarding claim 33, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., substantially the entirety of claimed subject matter, but do not explicitly state “further comprising, before forming the dielectric layer: forming a first shallow-trench isolation (STI) structure within the peripheral region of the substrate; and forming a second STI structure within the device region of the substrate, wherein at least one of the active TSV openings extends through the first STI structure, and at least one of the dummy via openings is aligned over the second STI structure”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Tsai and Lin with “further comprising, before forming the dielectric layer: forming a first shallow-trench isolation (STI) structure within the peripheral region of the substrate; and forming a second STI structure within the device region of the substrate, wherein at least one of the active TSV openings extends through the first STI structure, and at least one of the dummy via openings is aligned over the second STI structure”, since Tsai teaches all sorts of insulating layers and optional hard mask layers before forming of dielectric layer (pars. 27-28), the cited STI layers are well within the scope of those “hard mask” teachings of Tsai; thus, resulting with various STI structures in combined device.
Regarding claim 34, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., wherein forming the metal layer includes forming:
an active TSV of the plurality of active TSVs having a first height and a first width at a top surface of the active TSV; and a dummy via of the plurality of dummy vias having a second height and a second width at a top surface of the dummy via, wherein the first height is greater than the second height, and the first width is greater than the second width (see claim 21 for width; see claim 16 for discussion of height).
Regarding claim 35, the combined method of Tsai and Lin disclose in cited figures and related text, e.g., but do not explicitly state “wherein forming the plurality of dummy vias comprises forming a plurality of clusters of dummy vias, wherein: centers of adjacent dummy vias within each cluster are spaced apart by a first distance; and adjacent clusters are spaced apart by a second distance greater than the first distance”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the method of Tsai and Lin with “wherein forming the plurality of dummy vias comprises forming a plurality of clusters of dummy vias, wherein: centers of adjacent dummy vias within each cluster are spaced apart by a first distance; and adjacent clusters are spaced apart by a second distance greater than the first distance”, since the Lin’s dummy TSVs are used for heat dissipation, and it is notoriously well-known that not all areas of the chip are equally hot; thus, a skilled artisan would deposit the clusters of TSVs (Lin shows his TSVs as a cluster), in places that run most hot; thus resulting in spacing between clusters, for example when two hot spots are on opposite sides of device region.
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Alexander Belousov/Patent Examiner, Art Unit 2894
09/20/26
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights