DETAILED ACTION
This Action is responsive to the communication filed on 03/13/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claim 20 is objected to because of the following informalities: line 2 recites the limitation: “patterning a opening” (emphasis added). The claimed limitation should recite patterning an opening. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 12, and 16-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Strong (US 2020/0294901).
Regarding claim 1, Strong (see, e.g., FIG. 2B) discloses a device comprising:
a redistribution structure 240 (bottom); 210b [far left under 230 (left)], 211 [far left under 230 (left)]; 210b [far right under 230 (left)], 211 [far right under 230 (left)]; 210a [under 230 (left)]; 240 (top); 230 (left) comprising:
a first dielectric layer 240 (bottom) (Para 0045, Para 0046, Para 0050, Para 0051);
a first grounding feature 210b [far left under 230 (left)], 211 [far left under 230 (left)] on the first dielectric layer 240 (bottom), the first grounding feature 210b [far left under 230 (left)], 211 [far left under 230 (left)] comprising a first conductive line 210b [far left under 230 (left)] and a first conductive via 211 [far left under 230 (left)] on the first conductive line 210b [far left under 230 (left)] (Para 0045, Para 0046, Para 0050, Para 0051);
a second grounding feature 210b [far right under 230 (left)], 211 [far right under 230 (left)] on the first dielectric layer 240 (bottom), the second grounding feature 210b [far right under 230 (left)], 211 [far right under 230 (left)] comprising a second conductive line 210b [far right under 230 (left)] and a second conductive via 211 [far right under 230 (left)] on the second conductive line 210b [far right under 230 (left)] (Para 0045, Para 0046, Para 0050, Para 0051);
transmission lines 210a [under 230 (left)] on the first dielectric layer 240 (bottom), the transmission lines 210a [under 230 (left)] disposed between the first grounding feature 210b [far left under 230 (left)], 211 [far left under 230 (left)] and the second grounding feature 210b [far right under 230 (left)], 211 [far right under 230 (left)] (Para 0045, Para 0046, Para 0050, Para 0051);
a second dielectric layer 240 (top) on the transmission lines 210a [under 230 (left)] and the first dielectric layer 240 (bottom), a top surface of the second dielectric layer 240 (top) being planar with a top surface of the first conductive via 211 [far left under 230 (left)] and a top surface of the second conductive via 211 [far right under 230 (left)] (Para 0045, Para 0046, Para 0050, Para 0051); and
a third grounding feature 230 (left) on the top surface of the second dielectric layer 240 (top), the third grounding feature 230 (left) contacting the top surface of the first conductive via 211 [far left under 230 (left)] and the top surface of the second conductive via 211 [far right under 230 (left)] (Para 0045, Para 0046, Para 0050, Para 0051).
Regarding claim 2, Strong (see, e.g., FIG. 2B) teaches the device of claim 1, wherein the transmission lines 210a [under 230 (left)] are separated from the first grounding feature 210b [far left under 230 (left)], 211 [far left under 230 (left)] and from the second grounding feature 210b [far right under 230 (left)], 211 [far right under 230 (left)] by a first distance e.g., distance between 210a [under 230 (left)] and 210b [far left under 230 (left)], 211 [far left under 230 (left)]; 210b [far right under 230 (left)], 211 [far right under 230 (left)], the transmission lines 210a [under 230 (left)] are separated from one another by a second distance e.g., distance between adjacent 210a [under 230 (left)], and the second distance e.g., distance between adjacent 210a [under 230 (left)] is different than the first distance e.g., distance between 210a [under 230 (left)] and 210b [far left under 230 (left)], 211 [far left under 230 (left)]; 210b [far right under 230 (left)], 211 [far right under 230 (left)].
Regarding claim 3, Strong (see, e.g., FIG. 2B) teaches the device of claim 2, wherein the second distance e.g., distance between adjacent 210a [under 230 (left)] is greater than twice the first distance e.g., distance between 210a [under 230 (left)] and 210b [far left under 230 (left)], 211 [far left under 230 (left)]; 210b [far right under 230 (left)], 211 [far right under 230 (left)].
Regarding claim 12, Strong (see, e.g., FIG. 2B) discloses a device comprising:
a redistribution structure 231; 240 (bottom); 210b [far left under 230 (left)], 211 [far left under 230 (left)]; 210b [far right under 230 (left)], 211 [far right under 230 (left)]; 210a [under 230 (left)]; 240 (top); 230 (left), 230 (right) comprising:
a first metallization pattern 231 comprising a first grounding plane 231 (Para 0050, Para 0051);
a first dielectric layer 240 (bottom) on the first metallization pattern 231 (Para 0045, Para 0046, Para 0050, Para 0051);
a second metallization pattern 210b [far left under 230 (left)], 211 [far left under 230 (left)]; 210b [far right under 230 (left)], 211 [far right under 230 (left)]; 210a [under 230 (left)] comprising a first grounding feature 210b [far left under 230 (left)], 211 [far left under 230 (left)], a second grounding feature 210b [far right under 230 (left)], 211 [far right under 230 (left)], and transmission lines 210a [under 230 (left)] on the first dielectric layer 240 (bottom), the transmission lines 210a [under 230 (left)] horizontally disposed between the first grounding feature 210b [far left under 230 (left)], 211 [far left under 230 (left)] and the second grounding feature 210b [far right under 230 (left)], 211 [far right under 230 (left)], the first grounding feature 210b [far left under 230 (left)], 211 [far left under 230 (left)] comprising a first conductive line 210b [far left under 230 (left)] and a first conductive via 211 [far left under 230 (left)] on the first conductive line 210b [far left under 230 (left)], the second grounding feature 210b [far right under 230 (left)], 211 [far right under 230 (left)] comprising a second conductive line 210b [far right under 230 (left)] and a second conductive via 211 [far right under 230 (left)] on the second conductive line 210b [far right under 230 (left)] (Para 0045, Para 0046, Para 0050, Para 0051);
a second dielectric layer 240 (top) on the transmission lines 210a [under 230 (left)] and the first dielectric layer 240 (bottom), a top surface of the second dielectric layer 240 (top) being planar with a top surface of the first conductive via 211 [far left under 230 (left)] and a top surface of the second conductive via 211 [far right under 230 (left)] (Para 0045, Para 0046, Para 0050, Para 0051); and
a third metallization pattern 230 (left), 230 (right) comprising a second grounding plane 230 (left) on the top surface of the second dielectric layer 240 (top), the top surface of the first conductive via 211 [far left under 230 (left)] of the first grounding feature 210b [far left under 230 (left)], 211 [far left under 230 (left)], and the top surface of the second conductive via 211 [far right under 230 (left)] of the second grounding feature 210b [far right under 230 (left)], 211 [far right under 230 (left)], the transmission lines 210a [under 230 (left)] vertically disposed between the first grounding plane 231 and the second grounding plane 230 (left) (Para 0045, Para 0046, Para 0050, Para 0051).
Regarding claim 16, Strong (see, e.g., FIG. 2A, FIG. 2B) discloses a method comprising:
depositing a first dielectric layer 240 (bottom) (Para 0050, Para 0051);
forming a first metallization pattern 210a; 210b; 211 on the first dielectric layer 240 (bottom), the first metallization pattern 210a; 210b; 211 comprising first transmission lines 210a [left two under 230 (left)], second transmission lines 210a [right two under 230 (left)], and a first grounding feature 210b [middle ground conductive trace under 230 (left)], 211 [middle via under 230 (left)], the first grounding feature 210b [middle ground conductive trace under 230 (left)], 211 [middle via under 230 (left)] disposed between the first transmission lines 210a [left two under 230 (left)] and the second transmission lines 210a [right two under 230 (left)], the first grounding feature 210b [middle ground conductive trace under 230 (left)], 211 [middle via under 230 (left)] having a first length e.g., length of 210b [middle ground conductive trace under 230 (left)], 211 [middle via under 230 (left)], the first transmission lines 210a [left two under 230 (left)] and the second transmission lines 210a [right two under 230 (left)] extending continuously along the first length e.g., length of 210b [middle ground conductive trace under 230 (left)], 211 [middle via under 230 (left)] of the first grounding feature 210b [middle ground conductive trace under 230 (left)], 211 [middle via under 230 (left)] (Para 0045, Para 0046, Para 0050, Para 0051; FIG. 2A);
depositing a second dielectric layer 240 (top) on the first metallization pattern 210a; 210b; 211 and the first dielectric layer 240 (bottom) (Para 0045, Para 0046, Para 0050, Para 0051); and
forming a second metallization pattern 230(left), 230 (right) having a second grounding feature 230 (left) on the second dielectric layer 240 (top) (Para 0045, Para 0046, Para 0050, Para 0051).
Regarding claim 17, Strong (see, e.g., FIG. 2A, FIG. 2B) teaches the method of claim 16, wherein the first grounding feature 210b [middle ground conductive trace under 230 (left)], 211 [middle via under 230 (left)] comprises a first conductive line 210b [middle ground conductive trace under 230 (left)] and a first conductive via 211 [middle via under 230 (left)] on the first conductive line 210b [middle ground conductive trace under 230 (left)], and a planar portion of the second grounding feature 230 (left) contacts a top surface of the first conductive via 211 [middle via under 230 (left)] (Para 0045, Para 0046, Para 0050, Para 0051).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Strong (US 2020/0294901), in view of Kim (US 2017/0278830).
Regarding claim 10, although Strong shows substantial features of the claimed invention, Strong fails to expressly teach the device of claim 1, further comprising: a semiconductor device, the transmission lines being electrically coupled to the semiconductor device.
Kim (see, e.g., FIG. 1B), in a similar field of endeavor, teaches a semiconductor device 120, the transmission lines 115s being electrically coupled to the semiconductor device 120 for the purpose of providing a device package (Para 0017, Para 0018).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Strong to include a semiconductor device as described by Kim for the purpose of providing a device package (Para 0017, Para 0018).
Allowable Subject Matter
Claims 4-9, 11, 13-15, and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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