DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 6 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Wu et al. (TW I724815B)
With respect to claim 1, Wu describes a method comprising: providing a spacer material layer 700 or claimed a first mask layer over and extending over sidewalls of the mask 220A’ and 220B’ or claimed a mask line to form a first mask 700A, 700B (fig 7, 8);
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etching a first hard mask layer 210 under the mask 220A and 200B using the mask spacers 700A and 700B as an etching mask to form a pattern mask 210A and 210B (fig. 12)
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; forming a pattern including a conductive patterned layer 102A, 102B, since these patterns have sidewalls, it would provide claimed pillars, and patterned gate layer 101A, 102B or claimed line under the conductive patterned layer 102A, 102B by an etch process (page 5; fig. 14).
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with respect to claim 2, the patterned conductive layer 102A, 102B, and patterned gate layer 101A and 101B comprises of conductive material (pages 2, 5).
With respect to claim 5, fig. 14 above shows conductive patterned layer 102A or claimed pillar has a smaller width than that of the patterned gate layer 101B or claimed the line.
With respect to claim 6, the second hard mask 220 or claimed mask line comprises of TEOS oxide (page 3) and the spacer layer 700 or claimed first mask comprises of different material such as polysilicon (page 4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu as applied to claim 6 above.
With respect to claims 7 and 8, Wu doesn’t describe the second mask 220 comprises of a nitride and the spacer layer 700 comprises of an oxide. However, using nitride and oxide as etching masks are also taught by Wu (pages 2, 3). He also describes “it is understandable that some embodiments of the present invention utilize the difference in etch selectivity among the first hard mask layer 210, the second hard mask layer 220, and the third hardmask layer 230, so as to improve the etch selectivity in the subsequent steps. The specific film layer is etched during the etching process (details will be discussed below). Therefore, the materials of each film layer in the hard mask stack 200 mentioned here are only exemplary, and suitable mask materials can be matched according to the process conditions, and the embodiments of the present invention are not limited thereto.” Therefore, it would have been obvious for one skilled in the art to use materials such as nitride and oxide for the second mask 220 and spacer layer 700 as long as they provide etching masks to etch underlayers with expected results.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu as applied to claim 2 above, and further in view of Fan et al. (US 2023/0422520).
With respect to claim 3, Wu doesn’t describe that the conductive pattern layer 102A, 102B and the patterned gate layer 101A and 101B comprises of ruthenium. However, using ruthenium as conductive material to form memory cells is practiced by one skilled in the art as shown here by Fan et al. (US 2023/0422520). Fan teaches that ruthenium along with other conductive materials including metals and metal nitride of tungsten, tantalum nitride, titanium nitride, which are also taught by Wu for making flash memory structure (page 2, 5), are known and used in the process of making flash memory (para 125). Therefore, it would have been obvious for one skilled in the art before the effective filing date of the invention to modify Wu’s process by using such conductive materials including ruthenium as conductive material for the conductive pattern layer 102A, 102B and the patterned gate layer 101A and 101B in order to provide a semiconductor structure with expected results.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. With respect to claim 4, Wu doesn’t teach nor suggest that the spacer material layer 700 or first mask comprises a round shape in a top view.
Claim 9 and its dependent claims 10-19 are allowed because Wu doesn’t teach a pillar mask over a line of a tone inversion mask, transfer a pattern of the pillar mask and the tone inversion mask to a lower hardmask layer and etching a conductive layer under the patterned lower hardmask by using the patterned lower hardmask layer as an etching, the etching forming a line a pillar over the line.
Claim 20 and its dependent claims 21-23 are allowed because Wu doesn’t teach the steps of “forming a pillar mask over a mask line, the mask line being over a hardmask layer, the hardmask layer covering a conductive layer; forming a patterned hardmask by transferring a pattern of the pillar mask and the mask line to the hardmask layer; removing a portion of the mask line, a remaining portion of the mask line being covered by the pillar mask; removing the pillar mask”; consequently, he fails to teach the steps of “etching the conductive layer using the remaining portion of the mask line and the patterned hardmask as a first etch mask; removing a portion of the patterned hardmask, a remaining portion of the patterned hardmask being covered by the remaining portion of the mask line; and forming a conductive pillar over a conductive line by further etching the conductive layer using the remaining portion of the patterned hardmask as a second etch mask, the conductive pillar being under the second etch mask.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY VU NGUYEN DEO whose telephone number is (571)272-1462. The examiner can normally be reached 9-5 M-F.
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/DUY VU N DEO/Primary Examiner, Art Unit 1713
1/22/2026