DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 03/13/2024.
Claims 1-19 are pending in this application.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 03/13/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Foreign Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
4. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsuda et al. (US 2024/0237435)
Regarding claim 1, Tsuda discloses a display device comprising:
a substrate 310 (see fig. 17, fig. 19);
a field effect transistor 300 on the substrate 310;
an oxide-based transistor 200 (fig. 17) or 500 (fig. 19, see also paras. 0544, 0057) on a layer different from the field effect transistor 300 and connected to the field effect transistor 300 through a contact hole 214, 216, 376 in an insulating layer 210-222; and
a pixel electrode 122 (122a, 122b) on the oxide-based transistor.
Regarding claim 2, Tsuda discloses the display device of claim 1, wherein the field effect transistor 300 comprises a metal-oxide-semiconductor field effect transistor (MOSFET). See paras. 0451-0453.
Regarding claim 3, Tsuda discloses the display device of claim 1, wherein the substrate 310 comprises a silicon substrate. Para. 0449.
Regarding claim 4, Tsuda discloses the display device of claim 1, wherein the field effect transistor 300 comprises a driving transistor comprising a gate electrode connected to a first node, a source electrode connected to a driving voltage line, and a drain electrode connected to a second node. See figs. 17, 19, and paras. 0451-0458.
Regarding claim 5, Tsuda discloses the display device of claim 4, wherein the field effect transistor 300 further comprises an emission control transistor comprising a gate electrode connected to an emission control line, a source electrode connected to the second node, and a drain electrode connected to the pixel electrode. See figs. 17, 19, and paras. 0451-0458.
Regarding claim 6, Tsuda discloses the display device of claim 5, wherein the field effect transistor 300 further comprises an initialization transistor comprising a gate electrode connected to a third gate line, a source electrode connected to the pixel electrode, and a drain electrode connected to a ground. See figs. 17, 19, and paras. 0213, 0451-0458.
Regarding claim 7, Tsuda discloses the display device of claim 4, wherein the oxide-based transistor 200/500 comprises a switching transistor 500A (fig. 25A) comprising a gate electrode connected to a first gate line GL1, a drain electrode connected to a data line SL, and a source electrode connected to the first node.
Regarding claim 8, Tsuda discloses the display device of claim 7, wherein the oxide-based transistor 200/500 further comprises a compensation transistor 500D comprising a gate electrode connected to a second gate line GL3, a drain electrode connected to the first node, and a source electrode connected to the second node. See fig. 27A.
Regarding claim 9, Tsuda discloses the display device of claim 7, further comprising a first capacitor 600 (fig. 25) connected between the driving voltage line V0 and the first node.
Regarding claim 10, Tsuda discloses the display device of claim 9, further comprising a second capacitor 600A connected between the source electrode of the switching transistor and the first node. See fig. 27B.
Regarding claim 11, Tsuda discloses the display device of claim 10, wherein the first capacitor 600 and the second capacitor 600A are on the oxide-based transistor.
Regarding claim 12, Tsuda discloses the display device of claim 4, wherein the driving transistor 500 (500A, 500B) comprises a dual gate transistor. See fig. 25A.
Regarding claim 13, Tsuda discloses the display device of claim 1, wherein the field effect transistor comprises a P-type transistor. See paras. 0031, 0453.
Regarding claim 14, Tsuda discloses the display device of claim 1, wherein the oxide-based transistor comprises an N-type transistor. See paras. 0485, 0544-0548.
Regarding claim 15, Tsuda discloses the display device of claim 1, wherein an active layer of the oxide-based transistor comprises indium-gallium-zinc oxide (IGZO) or indium-gallium-zinc-tin oxide (IGZTO). See para. 0550.
Regarding claim 16, Tsuda discloses the display device of claim 1, wherein the oxide-based transistor 200/500 is located farther from the substrate 310 than the field effect transistor 300 is. See figs. 17, 19.
Regarding claim 17, Tsuda discloses the display device of claim 1, wherein the pixel electrode 122a is connected to the field effect transistor 30 (via conductive via 216 and transistor 200/500). See figs. 17, 19.
Regarding claim 18, Tsuda discloses the display device of claim 1, wherein the field effect transistor is a double gate transistor. See fig. 25A.
Regarding claim 19, Tsuda discloses the display device of claim 1, wherein the field effect transistor overlaps the oxide-based transistor. See figs. 17, 19.
Conclusion
7. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 June 26, 2026
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