DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/20/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In Claim 1, lines 9-10, the recitations of “the controller adjusts at least one first element parameter of the first terminal signal circuit or at least one second element parameter of the second terminal signal circuit based on a transmitted differential signal at a second terminal of the transmission path” is unclear because the controller does not appear receiving any signal from the differential output in order to adjust at least one second element parameter of the second terminal signal circuit based on a transmitted differential signal at a second terminal of the transmission path. Further clarification .
Claims 13 is rejected in the same manner as discussed in claim 1.
Claims 2-12 and 14-16 are rejected due to their dependency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, 10-11 & 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maeda et al. (US 20150002205 A1, hereinafter called Maeda).
Regarding claims 1 & 13:
Maeda discloses in Fig. 2, a differential amplification device or method, configured to generate a differential output signal to a first terminal of a transmission path, the differential amplification device comprising:
a first terminal signal circuit (form by transistors 101 and 105), configured to generate a first terminal signal (a signal provide to gate terminal of transistor 34) in the differential output signal;
a second terminal signal circuit (forms by transistors 102, 106), coupled to the first terminal signal circuit (transistors 101 and 102 both connected to same supply Vdd and transistors 105, 106 both connected to a common ground), wherein the second terminal signal circuit generates a second terminal signal (a signal which provide to gate terminal of transistor 33) in the differential output signal; and
a controller (forms by control circuit 109, ADCs 107, 108 and DACs 110 & 111), coupled to the first terminal signal circuit and the second terminal signal circuit, wherein the controller adjusts at least one first element parameter (control the variable resistors 103, transistor 105) of the first terminal signal circuit or at least one second element parameter (control variable resistor 104, transistor 106) of the second terminal signal circuit based on a transmitted differential signal at a second terminal of the transmission path (note that the controller which connected between differential output terminal, drain of transistor 101 and drain of transistor 102) , so as to compensate for asymmetric influence by the transmission path on a first terminal signal and a second terminal signal in the transmitted differential signal, wherein adjustment of the at least one first element parameter of the first terminal signal circuit is independent of adjustment of the at least one second element parameter of the second terminal signal circuit (see [0093], the positive signal and the negative signal are independently changed).
Regarding claims 2 & 14:
Maeda discloses in Fig. 2, wherein the first terminal signal circuit comprises: a load circuit (resistors 103, 103), having a first terminal (a terminal of resistor 103) coupled to a first voltage (Vdd), wherein a second terminal (other terminal) of the load circuit is coupled to an output terminal (drain terminal of transistor 101) of the first terminal signal circuit, and the output terminal provides the first terminal signal;
an amplification circuit (transistor 101), having an input terminal (gate terminal) configured to receive a first terminal signal (signal at terminal 202) in a differential input signal of the differential amplification device, wherein a first current terminal (drain terminal of transistor 101) of the amplification circuit is coupled to the second terminal of the load circuit; and
a current source (e.g., transistor 105), coupled to a second current terminal (source terminal of transistor 101) of the amplification circuit, wherein the at least one first element parameter (resistor 103) comprises impedance of the load circuit (resistors 103, 104), a gain of the amplification circuit, or a current value of the current source.
Regarding claim 3:
Maeda discloses in Fig. 2, wherein the load circuit comprises: a variable resistor (resistors 103, 104), controlled by the controller, wherein a first terminal (a terminal of resistor 103) of the variable resistor is coupled to the first voltage (Vdd), and a second terminal (other terminal of resistor 103) of the variable resistor is coupled to an output terminal (a terminal between drain of transistor 101 and resistor 103) of the first terminal signal circuit.
Regarding claim 4:
Maeda discloses in Fig. 2, wherein the amplification circuit comprises: an amplification unit (transistor 101), wherein a first current terminal (drain terminal of transistor 101) of the amplification unit is coupled to the second terminal of the load circuit (resistors 103, 104), and a second current terminal (source terminal of transistor 101) of the amplification unit is coupled to the current source (transistor 106); and
a pushing unit (transistor 24), having an output terminal (drain terminal) coupled to a control terminal (gate terminal of transistor 101) of the amplification unit, wherein an input terminal (gate terminal of transistor 24) of the pushing unit is configured to receive the first terminal signal (202) in the differential input signal.
Regarding claim 7:
Maeda discloses in Fig. 2, wherein the second current terminal (source terminal of transistor 101) of the amplification circuit of the first terminal signal circuit is coupled to a second current terminal (source terminal of transistor 101) of an amplification circuit of the second terminal signal circuit (both source terminals of transistors 101 and 102 connected to the common ground).
Regarding claims 10 & 15:
Maeda discloses wherein in response to attenuation of the first terminal signal of the transmitted differential signal by the transmission path being greater than attenuation of the second terminal signal of the transmitted differential signal by the transmission path, the controller (controller 109, ADC 107, 108 and ADC 110, 111) reduces a first current value of a first current source (transistor 105) of the first terminal signal circuit, or the controller reduces a first gain of a first amplification circuit (resistor 103, transistors 101, 105) of the first terminal signal circuit, or the controller (controller 109, ADC 107, 108 and ADC 110, 111, which adjust the impedance of the load) reduces first impedance of a first load circuit (resistor 103) of the first terminal signal circuit, or the controller (controller 109, ADC 107, 108 and ADC 110, 111) reduces the first current value and the first gain (control the current source, transistor 105), or the controller (controller 109, ADC 107, 108 and ADC 110, 111) reduces the first gain and the first impedance, or the controller (controller 109, ADC 107, 108 and ADC 110, 111) reduces the first current value, the first gain and the first impedance; and in response to the attenuation of the first terminal signal of the transmitted differential signal by the transmission path being less than the attenuation of the second terminal signal of the transmitted differential signal by the transmission path, the controller (controller 109, ADC 107, 108 and ADC 110, 111) reduces a second current value of a second current source of the second terminal signal circuit, or the controller reduces a second gain of a second amplification circuit of the second terminal signal circuit, or the controller (controller 109, ADC 107, 108 and ADC 110, 111) reduces second impedance of a second load circuit of the second terminal signal circuit, or the controller (controller 109, ADC 107, 108 and ADC 110, 111) reduces the second current value and the second gain, or the controller reduces the second gain and the second impedance, or the controller (controller 109, ADC 107, 108 and ADC 110, 111) reduces the second current value, the second gain and the second impedance.
Regarding claims 11 & 16:
Maeda discloses wherein the first terminal signal circuit comprises: a load circuit (load resistor 103), having a first terminal (a terminal) coupled to a first voltage (Vdd), wherein a second terminal (another terminal) of the load circuit is coupled to an output terminal (drain terminal of transistor 101) of the first terminal signal circuit, and the output terminal provides the first terminal signal; and
an amplification circuit (transistor 101), having an input terminal (gate terminal of transistor 101) configured to receive a first terminal signal in a differential input signal of the differential amplification device, wherein a first current terminal (drain terminal of transistor 101) of the amplification circuit is coupled to the second terminal of the load circuit (resistor 103), wherein the at least one first element parameter (resistor 103) comprises impedance of the load circuit or a gain of the amplification circuit.
Claims 1, 9 & 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Roo et al. (US 7312662 B1, hereinafter called Roo).
Regarding claims 1 & 13:
Roo discloses in Fig. 3, a differential amplification device or method, configured to generate a differential output signal to a first terminal of a transmission path, the differential amplification device comprising:
a first terminal signal circuit (circuit 205), configured to generate a first terminal signal (drain terminal of Q2) in the differential output signal;
a second terminal signal circuit (230), coupled to the first terminal signal circuit, wherein the second terminal signal circuit generates a second terminal signal (drain terminal of Q4) in the differential output signal; and
a controller (forms (circuits 288, 287), coupled to the first terminal signal circuit (205) and the second terminal signal circuit (230), wherein the controller adjusts at least one first element parameter (control Q2) of the first terminal signal circuit (205) or at least one second element parameter of the second terminal signal circuit based on a transmitted differential signal at a second terminal of the transmission path, so as to compensate for asymmetric influence by the transmission path (Ro+) on a first terminal signal and a second terminal signal (Ro- in the transmitted differential signal, wherein adjustment of the at least one first element parameter (transistor Q2) of the first terminal signal circuit (205) is independent of adjustment of the at least one second element parameter (Q4) of the second terminal signal circuit.
Regarding claim 9:
Roo discloses in Fig. 3 further comprising: a resistor (RTX), wherein a first terminal (top terminal of the resistor RTX) of the resistor is coupled to a first output terminal (drain terminal of Q2) of the first terminal signal circuit (205), and a second terminal (bottom terminal of resistor RTX) of the resistor is coupled to a second output terminal (drain terminal of Q4) of the second terminal signal circuit.
Allowable Subject Matter
Claims 5-6, 8 & 12 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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