DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statements (IDS) filed on 14 March 2024 and 11 July 2024. The references cited on the PTOL 1449 forms have been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 10, it’s unclear as to what applicant means by “binding energy of the metal oxide.” The applicant’s written description does not provide for particular metal oxide materials for the insulating layer that necessarily exhibit this binding energy comparison. The applicant’s disclosure regarding binding energy is with respect to the presence of elements in the semiconductor stack structure and not the metal oxide insulating layer itself (par. 72-75).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6, 7, 12, 15, 17 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (U.S. Patent Application Publication 2012/0238046).
Referring to Claim 1, Yu teaches a light emitting element (100) comprising: a semiconductor stack structure (101-103; par. 20; GaN based) including: an N-type semiconductor layer (102; GaN); a P-type semiconductor layer (101; GaN); and an active layer (103) disposed between the N-type semiconductor layer (102) and the P-type semiconductor layer (101); and an insulating layer (106; par. 21) disposed on a side portion of the semiconductor stack structure (101-103), wherein the semiconductor stack structure (101-103) further includes a fluorinated area (110; formed by ions 109; par. 24; fluorine) disposed adjacent to the insulating layer (106).
Referring to Claim 2, Yu inherently teaches wherein the fluorinated area (110; formed by fluorine ions 109) of the semiconductor stack structure (GaN based) comprises GaFxN(1-x). It is noted that this recitation also encompasses GaN alone, even without the presence of fluorine, when x = 0.
Referring to Claim 3, Yu teaches wherein the fluorinated area (110) has a non-uniform fluorine (F) concentration gradient (Gaussian Profile) with respect to depth from an outer surface of the semiconductor stack structure (101-103) (par. 25-28).
Referring to Claim 6, Yu further teaches wherein the fluorinated area (110) covers an entirety of the side portion of the semiconductor stack structure (101-103) (par. 31).
Referring to Claim 7, Yu further teaches wherein the fluorinated area (110) covers a side portion (right side) of the P-type semiconductor layer (101) and a side portion (right side) of the active layer (103), and the fluorinated area (110) does not cover a side portion (left side) of the N-type semiconductor layer (102).
Referring to Claim 12, Yu teaches a display device, comprising: a base layer (104); and a light emitting element (100) disposed on the base layer (104), wherein the light emitting element (100) includes a semiconductor stack structure (101-103) and an insulating layer (106) disposed on a side surface of the semiconductor stack structure (106), the semiconductor stack structure (106) including an N-type semiconductor layer (101), a P-type semiconductor layer (102), and an active layer (103) disposed between the N-type semiconductor layer (102) and the P-type semiconductor layer (101), and the semiconductor stack structure (101-103) further includes a fluorinated area (110) disposed adjacent to the insulating layer (106).
Referring to Claim 15, Yu inherently teaches wherein the fluorinated area (110; formed by fluorine ions 109) of the semiconductor stack structure (GaN based) comprises GaFxN(1-x). It is noted that this recitation also encompasses GaN alone, even without the presence of fluorine, when x = 0.
Referring to Claim 17, Yu teaches a method of manufacturing a light emitting element, the method comprising: forming a semiconductor stack layer (101-103) on a growth substrate (104); patterning the semiconductor stack layer (101-103); forming a fluorinated area (110) on a side surface of the patterned semiconductor stack structure (101-103); and forming an insulating layer (106) on the side surface of the patterned semiconductor stack structure (101-103).
Referring to Claim 18, Yu further teaches wherein the forming of the fluorinated area (110) includes providing fluorine (F) (109) to the patterned semiconductor stack structure (101-103) using an ion implantation technique and/or a surface treatment technique.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4, 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (U.S. Patent Application Publication 2012/0238046).
Referring to Claims 4 and 5, Yu teaches the limitations of claim 3, but does not explicitly state wherein the fluorinated area has a peak concentration of fluorine (F) at a depth in a range of about 0.001 μm to about 0.01 μm from the outer surface of the semiconductor stack structure (claim 4) and wherein the peak concentration is in a range of about 1.2x1018 [number/cm3] to about 1.6x1018 [number/cm3] (claim 5).
However, Yu does teach adjusting the thickness of the insulating layer and/or implant angle and/or implant energy and/or number of implant steps to achieve the desired depth of the ion implantation (Rp) (par. 25-29).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to adjust the peak concentration depth and concentration to be in the claimed ranges in order to provide the desired isolation and passivation to protect the LED from unexpected current leakage or control the effective current passing through an active region of the LED (par. 19), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Referring to Claim 16, Yu teaches the limitations of claim 15 wherein the fluorinated area (110) has a non-uniform fluorine (F) concentration gradient (Gaussian Profile) with respect to depth from an outer surface of the semiconductor stack structure (101-103) (par. 25-28), but does not explicitly state wherein the fluorinated area has a peak concentration of fluorine (F) at a depth in a range of about 0.001 μm to about 0.01 μm from the outer surface of the semiconductor stack structure, and the peak concentration is in a range from about 1.2x1018 [number/cm3] to about 1.6x1018 [number/cm3].
However, Yu does teach adjusting the thickness of the insulating layer and/or implant angle and/or implant energy and/or number of implant steps to achieve the desired depth of the ion implantation (Rp) (par. 25-29).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to adjust the peak concentration depth and concentration to be in the claimed ranges in order to provide the desired isolation and passivation to protect the LED from unexpected current leakage or control the effective current passing through an active region of the LED (par. 19), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (U.S. Patent Application Publication 2012/0238046) in view of Bour (U.S. Patent Application Publication 2018/0374991).
Referring to Claim 8, Yu teaches the limitations of claim 3, wherein the fluorinated area (110) is directly adjacent to the insulating layer (106) but does not explicitly state wherein the insulating layer (106) includes a metal oxide (par. 21).
In the same field of endeavor, Bour teaches wherein the insulating layer (170) includes a metal oxide (par. 76), and the doped area (150) is directly adjacent to the insulating layer (170).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to utilize metal oxide as taught by Bour as the insulating layer material of Yu in order to provide improved high quality thin film surface passivation (par. 76). It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. It is well settled that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. V. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945); In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960); Ritchie V. Vast Resources Inc. d/b/a Topco Sales, 90 USPQ2d 1668 (Fed. Cir. 2009); and MPEP § 2144.07.
Referring to Claim 9, as modified above, Bour further teaches wherein the metal oxide (170) comprises aluminum (Al) (par. 76).
As insofar as Claim 10 is definite, as modified above, Yu in view of Bour further inherently teaches the suitable materials disclosed by applicant, wherein a binding energy between fluorine (F) and gallium (Ga) is greater than a binding energy of the metal oxide (Al2O3). It’s unclear as to what applicant means by “binding energy of the metal oxide.” The applicant’s written description does not provide for particular metal oxide materials for the insulating layer that necessarily exhibit this binding energy comparison. The applicant’s disclosure regarding binding energy is with respect to the presence of elements in the semiconductor stack structure and not the metal oxide insulating layer itself (par. 72-75). As insofar as can be determined, it appears the prior art reference teaches the required structure that meets the binding energy property, otherwise the applicant’s disclosure is lacking sufficient written description support. “The claiming of a new use, new function or unknown property which is inherently present in the prior art does not necessarily make the claim patentable.” In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433 (CCPA 1977). (MPEP 2112). When the reference discloses all the limitations of a claim except a property or function, and the examiner cannot determine whether or not the reference inherently possesses properties which anticipate or render obvious the claimed invention but has basis for shifting the burden of proof to applicant as in In re Fitzgerald, 619 F.2d 67, 205 USPQ 594 (CCPA 1980).
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (U.S. Patent Application Publication 2012/0238046) in view of Lin et al. (U.S. Patent Application Publication 2022/0223755).
Referring to Claim 13, Yu teaches the limitations of claim 12 wherein the LED has anode and cathode electrodes respectively connected to the p-type and n-type semiconductor layers (par. 4) but does not explicitly show the electrodes. It appears to be inherent that the electrodes are all disposed on the base layer (104) (does not require each of the first and second electrodes to be in contact with the base layer), wherein the light emitting element (100) includes a first end and a second end, and the light emitting element is electrically connected to the first electrode at the first end and is electrically connected to the second electrode at the second end.
However, if one were to interpret the reference so narrowly that the each of the electrodes are not disposed on the base layer (104), Lin teaches in Fig. 9-14 for example, a first electrode (302) and a second electrode (305) disposed on the base layer (820), wherein the light emitting element includes a first end and a second end, and the light emitting element is electrically connected to the first electrode (302) at the first end and is electrically connected to the second electrode (305) at the second end.
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to provide electrodes as taught by Lin to the LED of Yu in order for the device to function as intended supplying the necessary charge carriers to the light emitting device.
Referring to Claim 14, Yu teaches the limitations of claim 12 wherein the LED has anode and cathode electrodes respectively connected to the p-type and n-type semiconductor layers (par. 4) but does not explicitly show the electrodes. It appears to be inherent that the electrodes are all disposed on the base layer (104) (does not require each of the first and second electrodes to be in contact with the base layer), a first alignment electrode and a second alignment electrode disposed on the base layer (104), wherein the light emitting element is aligned between the first alignment electrode and the second alignment electrode. “The identical invention must be shown in as complete detail as is contained in the ... claim.” Richardson v. Suzuki Motor Co., 868 F.2d 1226, 1236, 9 USPQ2d 1913, 1920 (Fed. Cir. 1989). The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990).
However, if one were to interpret the reference so narrowly that the each of the alignment electrodes are not disposed on the base layer (104), Lin teaches in Fig. 9-14 for example, a first alignment electrode (302) and a second alignment electrode (305) disposed on the base layer (820), wherein the light emitting element is aligned between the first alignment electrode (302) and the second alignment electrode (305).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to provide the alignment electrodes as taught by Lin to the LED of Yu in order for the device to function as intended supplying the necessary charge carriers to the light emitting device.
Allowable Subject Matter
Claims 11, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 11, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the the light emitting element wherein the insulating layer includes a first insulating layer disposed on the side portion of the semiconductor stack structure, and a second insulating layer disposed on the first insulating layer, the first insulating layer is disposed between the fluorinated area and the second insulating layer, each of the first insulating layer and the second insulating layer includes the metal oxide, the first insulating layer further includes fluorine (F), and the second insulating layer does not include fluorine (F) in combination with all of the limitations of Claims 17 and 19.
Regarding Claim 19, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the method wherein the forming of the insulating layer includes forming a plurality of insulating layers after the forming of the fluorinated area in combination with all of the limitations of Claims 17 and 19.
Regarding Claim 20, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the method wherein the forming of the insulating layer includes forming a first insulating layer on a side portion of the patterned semiconductor stack structure, and forming a second insulating layer on the first insulating layer, the forming of the first insulating layer is performed before the forming of the fluorinated area, and the forming of the second insulating layer is performed after the forming of the fluorinated area in combination with all of the limitations of Claims 17 and 20.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896
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