Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/29/2025 has been entered.
Allowable Subject Matter
The indicated allowability of claims 9-15 is withdrawn in view of the newly discovered reference(s) to Lee (an alternative interpretation). Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites the limitation “third width” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 22 is interpreted in the instant Office action as follows: “wherein the second width or third width” in line 2 and “at least one of the second width or the third width” in lines 4-5 are equivalent to “wherein the second width” and “the second width” based on antecedence in claim 16 and because we have no definition in the claim of what the third width could be related to or measured by. This interpretation is to be confirmed by applicant in the next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9-17 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20120146230 A1).
Regarding independent claim 9, Lee discloses a semiconductor structure (Fig. 3), comprising:
a first substrate (104) including a first plurality of conductive pads (217) that are laterally spaced apart from one another (See annotated figure for direction designation);
a first plurality of conductive bumps (332) disposed on the first plurality of conductive pads (directly on), respectively; and
a multi-tiered solder-resist structure (the collection of 206 with 208) comprising:
a first tier (206) comprising a first dielectric material ([0026]: “a non-conductive material”) and including first conductive bump openings (214) defined by inner sidewalls of the first tier (See annotated enlarged portion of Fig. 3), the first tier having a first width (left step width 329 of layer 206 + tier width 218 of layer 208 which vertically overlaps layer 206 + right step width 329 of layer 206, shorthand written as widths 329+218+329; See annotated figure for measurement annotations consistent with the top-down view of Fig. 2. Note: the width of 329 is disclosed as [0041]: “about 10 µm”; and width 218 is disclosed as 30-80 µm in equation (2) in [0034]. Thus, the first width is disclosed as 10 + 30 through 80 + about 10, or about 50-100 µm.) measured through the first dielectric material (as measured in the lateral direction) between the inner sidewalls of the first tier in a cross-sectional view (Fig. 3 is a cross-sectional view), the first tier having a bottom surface (a multi-planar bottom surface, See dashed reference line in enlarged portion of Fig. 3) that is coplanar to a top surface of the first plurality of conductive pads (See enlarged portion of Fig. 3) and that is coplanar to a surface of the first substrate (See enlarged portion of Fig. 3, separately coplanar with these two surfaces); and
a second tier (208) overlying the first tier (directly vertically overlying), the second tier comprising a second dielectric material ([0026]: “a non-conductive material”) and including second conductive bump openings (210) defined by inner sidewalls of the second tier (See annotated enlarged portion of Fig. 3), the second tier having a second width (218, See Fig. 2 or annotated Fig. 3 for measurement markings) measured through the second dielectric material between the inner sidewalls of the second tier in the cross-sectional view (Fig. 3 is a cross-sectional view);
wherein the first width ranges from 20 micrometers to 500 micrometers (as reasoned above, the 1st width is disclosed as about 50-100 µm, which is squarely within the claimed range), and wherein the second width is less than the first width and ranges from 18 micrometers to 450 micrometers (2nd width 218 is disclosed as 30-80 µm in equation (2) in [0034], which is squarely within the claimed range. Note: the separately cited ranges each have a plurality of selectable values capable of meeting the claim. For example, selecting 64 µm for the 2nd width 218, and 84 µm for the 1st width meets the claim).
Illustrated below are marked and annotated figures of Figs. 2 and 3, and a marked and annotated enlarged portion of Fig. 3 of Lee.
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Regarding claim 10, Lee discloses the semiconductor structure of claim 9 (Fig. 3): wherein a first conductive bump opening of the first conductive bump openings (opening 214 of Opening Group 1, See annotated figure) is axially aligned with a first conductive bump opening of the second conductive bump openings (opening 210 of Opening Group 1, See annotated figure) to define a first opening (Opening Group 1) extending through the first dielectric material (completely vertically through) and through the second dielectric material (completely vertically through), and a first conductive bump (a respective 332) is arranged within the first opening; wherein a second conductive bump opening of the first conductive bump openings (opening 214 of Opening Group 2, See annotated figure) is axially aligned with a second conductive bump opening of the second conductive bump openings (opening 210 of Opening Group 2, See annotated figure) to define a second opening (Opening Group 2) extending through the first dielectric material (completely vertically through) and through the second dielectric material (completely vertically through), and a second conductive bump (a respective 332) is arranged within the second opening.
Regarding claim 11, Lee discloses the semiconductor structure of claim 10, wherein nearest outer sidewalls defined by the first and second openings (See enlarged portion of Fig. 3) are spaced apart only by the first dielectric material and the second dielectric material (there are no other materials or structures intervening).
Regarding claim 12, Lee discloses the semiconductor structure of claim 10 (Fig. 3, enlarged portion), wherein the first dielectric material extends from a first inner sidewall (See annotated figure) to a second inner sidewall (See annotated figure) along a lateral plane (See annotated figure for direction designation) without any conductive features intersecting the lateral plane (the cited portion of 206 has no structures included in it, conductive or otherwise), wherein the first inner sidewall is defined by the first conductive bump opening of the first conductive bump openings (the cited sidewall is the same sidewall disclosed for opening 214 of Opening Group 1) and the second inner sidewall is defined by the second conductive bump opening of the first conductive bump openings (the cited sidewall is the same sidewall disclosed for opening 214 of Opening Group 2).
Regarding claim 13, Lee discloses the semiconductor structure of claim 12 (Fig. 3), wherein the second dielectric material extends over the first dielectric material (directly over), and wherein outer edges of the first and second conductive bumps overlie (vertically overlie at least indirectly) outer edges of an upper surface of the second dielectric material.
Regarding claim 14, Lee discloses the semiconductor structure of claim 9, further comprising: a second substrate (102) including a second plurality of conductive pads (330) that are laterally spaced apart from one another on the second substrate, wherein the first plurality of conductive bumps couple (directly couple) the second plurality of conductive pads to the first plurality of conductive pads.
Regarding claim 15, Lee discloses the semiconductor structure of claim 14 (Fig. 3), wherein an upper surface of the multi-tiered solder-resist structure is spaced apart from a lower surface of the second substrate by a gap (See annotated figure), and further comprising: a molding material (336) disposed over the first substrate and filling the gap (completely filling).
Regarding independent claim 16, Lee discloses a semiconductor structure (Fig. 3), comprising: a first substrate (104) including a first plurality of conductive pads (217) that are laterally spaced apart from one another (See annotated figure for direction designation);
a first plurality of conductive bumps (332) disposed on the first plurality of conductive pads (directly on), respectively; and
a multi-tiered solder-resist structure (the collection of 206 with 208) comprising:
a first tier (206) comprising a first dielectric material ([0026]: “a non-conductive material”) and including first conductive bump openings (214) having a first opening width (216, See Fig. 2 for measurement markings) defined by inner sidewalls of the first tier (See annotated enlarged portion of Fig. 3), the first tier having a first width (left step width 329 of layer 206 + tier width 218 of layer 208 which vertically overlaps layer 206 + right step width 329 of layer 206, shorthand written as widths 329+218+329; See annotated figure for measurement annotations consistent with the top-down view of Fig. 2. Note: the width of 329 is disclosed as [0041]: “about 10 µm”; and width 218 is disclosed as 30-80 µm in equation (2) in [0034]. Thus, the first width is disclosed as 10 + 30 through 80 + about 10, or about 50-100 µm.) measured through the first dielectric material (as measured in the lateral direction) between the inner sidewalls of the first tier in a cross-sectional view (Fig. 3 is a cross-sectional view); and
a second tier (208) overlying the first tier (directly vertically overlying), the second tier comprising a second dielectric material ([0026]: “a non-conductive material”) and including second conductive bump openings (210) having a second opening width (212, See Fig. 2 for measurement markings) defined by inner vertical sidewalls of the second tier (See annotated enlarged portion of Fig. 3), the second tier having a second width (218, See Fig. 2 or annotated Fig. 3 for measurement markings) measured through the second dielectric material between the inner vertical sidewalls of the second tier in the cross-sectional view (Fig. 3 is a cross-sectional view);
wherein a conductive bump of the of the first plurality of conductive bumps has a downwardly-facing surface (a curved barrel-shaped surface of bump 332, See annotated Fig. 3) that extends at least partially over a top surface of the second tier (indirectly vertically over) so the downwardly-facing surface of the conductive bump is co-planar with the top surface of the second tier (coplanar in the lateral/vertical plane shown as a cross-section for Fig. 3);
wherein the first opening width (opening 214 is disclosed having width 216 in equation (1) in [0030]: less than 60-80 µm) ranges from 20 micrometers to 500 micrometers (width 216 is squarely within this range), and wherein the second opening width (opening 210 is disclosed having width 212 in equation (1) in [0030]: greater than 80 µm) is greater than the first opening width (equation (1) in [0034] shows the “greater than” numerical relation) and ranges from 22 micrometers to 550 micrometers (width 212 is squarely within this range).
Regarding claim 17, Lee discloses the semiconductor structure of claim 16 (Fig. 3), further comprising: a second substrate (102) including a second plurality of conductive pads (330) that are laterally spaced apart from one another on the second substrate, wherein the first plurality of conductive bumps couple (directly couple) the second plurality of conductive pads to the first plurality of conductive pads.
Regarding claim 22, Lee discloses the semiconductor structure of claim 16 (Fig. 3), wherein the second width is measured along a lateral plane (a lateral direction was already designated in the claim 16 rejection), and wherein the conductive bump has a bump width (See annotated figure) as measured between outermost sidewalls of the conductive bump along the lateral plane (Bump 332 within opening 210 has a width matching width 212 of opening 210; this width is disclosed as greater than 80 µm in equation (1) in [0030]. Additionally, bump 332 has a barrel portion vertically above opening 210 wider than width 212. Thus bump 332 has a width wider than 80 µm), wherein the bump width is greater than the second width (the bump width is cited as greater than 80 µm, which is greater than the second width cited as 30-80 µm).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 17 above, and further in view of Huang (US 20190067231 A1).
Regarding claim 18, Lee discloses the semiconductor structure of claim 17, but fails to teach “a first die disposed over a first portion of the second substrate and connected to the second substrate through a first plurality of microbumps; and a second die disposed over a second portion of the second substrate and connected to the second substrate through a second plurality of microbumps”.
Huang discloses a second substrate (Fig. 9A: 82), and further discloses the second substrate configuration may be varied to include a plurality of configurations (the embodiments of Fig. 9A and Fig. 8, selecting the embodiment of Fig. 9A), including: a first die (84 on left, See annotated figure) disposed over a first portion of the second substrate (See annotated figure) and connected to the second substrate through a first plurality of microbumps (respective 85); and a second die disposed (84 on right, See annotated figure) over a second portion of the second substrate (See annotated figure) and connected to the second substrate through a second plurality of microbumps (respective 85).
Lee and Huang separately disclose each element claimed. One of ordinary skill in the art before the effective filing date could have combined the varied second substrate configuration of Huang with the second/first substrate configuration of Lee, and in combination each element merely performs the same function as it does separately (i.e. the second substrate performing the function of an integrated circuit). One of ordinary skill in the art before the effective filing date would have recognized that the results of the combination were predictable because: Huang teaches the second substrate performing the function of an integrated circuit (Huang: [0039]: “package… interposer… semiconductor dies”); and because Lee teaches configuration of the second substrate may be varied by disclosing a plurality of second substrate species configurations ([0025]: “a flip chip or an integrated circuit die”). One of ordinary skill in the art before the effective filing date would have been motivated to do so to produce a semiconductor structure having alternative functional utility, by the inclusion of additional components, i.e., a first and second die. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because it is a mere combination of prior art elements according to known second substrate configurations yielding a predictable semiconductor structure. MPEP 2143 (I)(A).
Regarding claim 19, Lee in view of Huang discloses the semiconductor structure of claim 18 (Lee: Fig. 3), wherein an upper surface of the multi-tiered solder-resist structure is spaced apart from a lower surface of the second substrate by a gap (See annotated figure), and further comprising: a molding material (336) disposed over the first substrate and filling the gap (completely filling).
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Shen (US 20100000775 A1).
Regarding claim 1, Lee discloses a semiconductor structure, (Fig. 3) comprising:
a first substrate (104) including a first plurality of conductive pads (217) that are laterally spaced apart from one another (See annotated figure for direction designation);
a first plurality of conductive bumps (332) disposed on the first plurality of conductive pads (directly on), respectively; and
a multi-tiered solder-resist structure (the collection of 206 with 208) comprising:
a first tier (206) comprising a first dielectric material ([0026]: “a non-conductive material”) and including first conductive bump openings (214) defined by inner sidewalls of the first tier, the first tier having a first width (left step width 329 of layer 206 + tier width 218 of layer 208 which vertically overlaps layer 206 + right step width 329 of layer 206, shorthand written as widths 329+218+329; See annotated figure for measurement annotations consistent with the top-down view of Fig. 2. Note: the width of 329 is disclosed as [0041]: “about 10 µm”; and width 218 is disclosed as 30-80 µm in equation (2) in [0034]. Thus, the first width is disclosed as 10 + 30 through 80 + about 10, or about 50-100 µm.) measured through the first dielectric material (as measured in the lateral direction) between the inner sidewalls of the first tier in a cross-sectional view (Fig. 3 is a cross-sectional view); and
a second tier (208) overlying the first tier (directly vertically overlying), the second tier comprising a second dielectric material ([0026]: “a non-conductive material”) and including second conductive bump openings (210) defined by inner sidewalls of the second tier, the second tier having a second width (width 218; this width is disclosed as 30-80 µm in equation (2) in [0034]) measured on a lateral plane through the second dielectric material between the inner sidewalls of the second tier in the cross-sectional view;
[…] and
wherein a conductive bump of the first plurality of conductive bumps has a bump width (See annotated figure) as measured between outermost sidewalls of the conductive bump along the lateral plane (Bump 332 within opening 210 has a width matching width 212 of opening 210; this width is disclosed as greater than 80 µm in equation (1) in [0030]. Additionally, bump 332 has a barrel portion vertically above opening 210 wider than width 212. Thus bump 332 has a width wider than 80 µm), wherein the bump width is greater than the second width of the second tier (the bump width is cited as greater than 80 µm, which is greater than the second width cited as 30-80 µm).
Lee fails to teach “a third tier overlying the second tier, the third tier comprising a third dielectric material and including third conductive bump openings defined by inner vertical sidewalls of the third tier, the third tier having a third width measured through the third dielectric material between the inner vertical sidewalls of the third tier in the cross-sectional view; wherein the third width is less than the second width”.
Shen teaches the number of tiers may be varied to achieve a required thickness of the multi-tiered solder-resist structure ([0053]: “In this embodiment, for example, two solder masks are stacked together. However, a solder mask with a required thickness may be formed by stacking a plurality of solder masks together”). One of ordinary skill in the art before the effective filing date could have varied the number of tiers of the multi-tiered solder-resist structure (of Lee) to include a third tier above the second tier based on Shen’s teachings of varying the number of tiers within a multi-tiered solder-resist structure to achieve a desired thickness. Doing so would arrive at the claimed number and configuration of tiers. One of ordinary skill in the art would have had predictable results because in each situation the multiple tiers perform the same function as a solder-resist structure (Shen: [0053]: “a solder mask”; Lee: [0026]: “resist layer” combined with [0046]: “solder”). The motivation to do so would be to have a multi-tiered solder-resist structure with different thickness. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed tier configuration because it would enable a solder-resist structure of an alternative design thickness. MPEP 2143 (I)(G).
Regarding claim 2, Lee in view of Shen discloses the semiconductor structure of claim 1 (Lee: Fig. 3): wherein a first conductive bump opening of the first conductive bump openings (opening 214 of Opening Group 1, See annotated figure) is axially aligned with a first conductive bump opening of the second conductive bump openings (opening 210 of Opening Group 1, See annotated figure) to define a first opening (Opening Group 1) extending through the first dielectric material (completely vertically through) and through the second dielectric material (completely vertically through); wherein a second conductive bump opening of the first conductive bump openings (opening 214 of Opening Group 2, See annotated figure) is axially aligned with a second conductive bump opening of the second conductive bump openings (opening 210 of Opening Group 2, See annotated figure) to define a second opening (Opening Group 2) extending through the first dielectric material (completely vertically through) and through the second dielectric material (completely vertically through).
Regarding claim 3, Lee in view of Shen discloses the semiconductor structure of claim 2 (Lee: Fig. 3), wherein the first opening and the second opening are spaced apart only by the first dielectric material and the second dielectric material (there are no other materials or structures intervening).
Regarding clam 4, Lee in view of Shen discloses the semiconductor structure of claim 2 (Lee: Fig. 3, enlarged portion), wherein the first dielectric material extends from a first inner sidewall (See annotated figure) to a second inner sidewall (See annotated figure) along a lateral plane (See annotated figure for direction designation) without any conductive features intersecting the lateral plane (the cited portion of 206 has no structures included in it, conductive or otherwise), wherein the first inner sidewall is defined by the first conductive bump opening of the first conductive bump openings (the cited sidewall is the same sidewall disclosed for opening 214 of Opening Group 1) and the second inner sidewall is defined by the second conductive bump opening of the first conductive bump openings (the cited sidewall is the same sidewall disclosed for opening 214 of Opening Group 2).
Regarding claim 5, Lee in view of Shen discloses the semiconductor structure of claim 4 (Lee: Fig. 3), further comprising: a first conductive bump (a corresponding 332) arranged within the first opening; and a second conductive bump (a corresponding 332) arranged within the second opening; wherein the second dielectric material extends over the first dielectric material (directly over), and wherein outer edges of the first and second conductive bumps overlie (vertically overlie at least indirectly) outer edges of an upper surface of the second dielectric material.
Regarding claim 6, Lee in view of Shen discloses the semiconductor structure of claim 1 (Lee: Fig. 3), further comprising: a second substrate (102) including a second plurality of conductive pads (330) that are laterally spaced apart from one another on the second substrate, wherein the first plurality of conductive bumps couple (directly couple) the second plurality of conductive pads to the first plurality of conductive pads.
Regarding claim 7, Lee in view of Shen discloses the semiconductor structure of claim 6 (Lee: Fig. 3), wherein an upper surface of the multi-tiered solder-resist structure is spaced apart from a lower surface of the second substrate by a gap (See annotated figure), and further comprising: a molding material (336) disposed over the first substrate and filling the gap (completely filling).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Shen as applied to claim 1 above, and further in view of Ji (KR 20220151431 A)
Regarding claim 21, Lee in view of Shen discloses the semiconductor structure of claim 1 (Lee: Fig. 3), wherein the conductive bump fills the first conductive bump opening (completely fills), fills the second conductive bump opening (completely fills), […]
Lee in view of Shen discloses the conductive bump but fails to teach a shape of the bump relative to the third tier. Thus, Lee in view of Shen fails to teach “wherein the conductive bump […] has a downwardly-facing surface that extends at least partially over a top surface of the third tier so the downwardly-facing surface of the conductive bump is co-planar with the top surface of the third tier”.
Ji discloses a conductive bump (Fig. 10: 710) and a third tier (See annotated figure) wherein the conductive bump […] has a downwardly-facing surface (a curved surface ultimately pointing in the downward direction along the dashed reference line) that extends at least partially over a top surface of the third tier (the curved portion is indirectly over) so the downwardly-facing surface of the conductive bump is co-planar with the top surface of the third tier (coplanar in the lateral/vertical plane shown as a cross-section for Fig. 10).
Modifying the shape of the conductive bump of Lee in view of Shen relative to the third tier to have the shape disclosed by Ji would arrive at the claimed shape configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success because in each case the conductive bump is configured among dielectric tiers (Lee: [0026]: “a non-conductive material”; Ji: pg. 5 of translation: “An insulating material”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed bump shape because it is a shape encompassed within the teachings of the prior art without any change in functional configuration. MPEP 2144.04 (IV)(B).
Response to Arguments
Applicant's arguments filed 12/29/2025 have been fully considered but they are not persuasive.
Applicant remarks:
Applicant remarks “claims 9-15 are allowed”. Remarks at pg. 9.
Examiner’s reply:
The examiner has provided an alternative interpretation of the Lee reference meeting the claim. Accordingly, allowability of the claims has been withdrawn.
Applicant argues:
Applicant argues with respect to amended claim 1 that “Previous claim 1 was rejected on the ground of nonstatutory double patenting […] Claim 1 has been amended”. Remarks at pg. 9.
Examiner’s reply:
The examiner finds the amendments in the instant set of claims overcomes the outstanding double patenting rejection because Wang does not claim directly or implicitly, or render obvious in the claims “wherein the bump width is greater than the second width of the second tier”.
Applicant argues:
Applicant argues with respect to amended claim 1 that “the width of the alleged bump 360 appears to be less than the width of the alleged second tier.”. Remarks at pg. 9.
Examiner’s reply:
Although the examiner agrees with Applicant’s remarks regarding the Shen reference, Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner has relied upon Lee to teach the contended limitation.
Applicant argues:
Applicant argues with respect to claims 16-20 that “Huang’s conductive bumps (e.g., 18 or 20) does not extend at least partially over a top surface of the second tier 10 so a downwardly-facing surface of the conductive bump 18 is co-planar with the top surface of the second tier 20”. Remarks at pg. 10.
Examiner’s reply:
The examiner does not find Applicant’s remarks persuasive because although Fig. 4E was cited, variations of Fig. 4E were relied upon to supplement the rejection (Fig. 3C). Regardless, Applicant’s arguments with respect to claim(s) 16-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The examiner has relied upon an alternative interpretation of Lee within the scope of MPEP 2111 regarding plane and direction orientations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817