Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/18/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 9 is objected to because of the following informalities: “the top surface of the first plurality of conductive pads” in line 12. For the sake of compact prosecution, claim 9 is interpreted in the instant Office action as follows: “the top surface of the first plurality of conductive pads” is found to be a typographical error and is believed to be equivalent to “a top surface of the first plurality of conductive pads”; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20120146230 A1).
Regarding independent claim 9, Lee discloses a semiconductor structure (Fig. 3), comprising:
a first substrate (104 grouped with subsequently cited structures 206/208) including a first plurality of conductive pads (217) that are laterally spaced apart from one another (See annotated figure for direction designation);
a first plurality of conductive bumps (332) disposed on the first plurality of conductive pads (directly on), respectively, the first plurality of conductive bumps having a top surface (See annotated enlarged portion of Fig. 3. Note: this surface is part of a “top” portion of the bump. Note: this interpretation is consistent with the required interpretation of Applicant’s disclosure to render the claim definite and supported by the original disclosure.) coplanar (laterally coplanar) to a surface of the first substrate (a surface of 1st tier 206. Note: this interpretation is consistent with the required interpretation of Applicant’s disclosure to render the claim definite and supported by the original disclosure.); and
a multi-tiered solder-resist structure (the collection of 206 with 208) comprising:
a first tier (206) comprising a first dielectric material ([0026]: “a non-conductive material”) and including first conductive bump openings (214) defined by inner sidewalls of the first tier (See annotated enlarged portion of Fig. 3), the first tier having a first width (left step width 329 of layer 206 + tier width 218 of layer 208 which vertically overlaps layer 206 + right step width 329 of layer 206, shorthand written as widths 329+218+329; See annotated figure for measurement annotations consistent with the top-down view of Fig. 2. Note: the width of 329 is disclosed as [0041]: “about 10 µm”; and width 218 is disclosed as 30-80 µm in equation (2) in [0034]. Thus, the first width is disclosed as 10 + 30 through 80 + about 10, or about 50-100 µm.) measured through the first dielectric material (as measured in the lateral direction) between the inner sidewalls of the first tier in a cross-sectional view (Fig. 3 is a cross-sectional view), the first tier having a planar bottom surface (a multi-planar bottom/downward facing surface, See dashed reference line in enlarged portion of Fig. 3) that is coplanar to the top surface of the first plurality of conductive pads (See enlarged portion of Fig. 3) and that is coplanar to the surface of the first substrate (See enlarged portion of Fig. 3, separately coplanar with these two surfaces); and
a second tier (208) overlying the first tier (directly vertically overlying), the second tier comprising a second dielectric material ([0026]: “a non-conductive material”) and including second conductive bump openings (210) defined by inner sidewalls of the second tier (See annotated enlarged portion of Fig. 3), the second tier having a second width (218, See Fig. 2 or annotated Fig. 3 for measurement markings) measured through the second dielectric material between the inner sidewalls of the second tier in the cross-sectional view (Fig. 3 is a cross-sectional view);
wherein the first width ranges from 20 micrometers to 500 micrometers (as reasoned above, the 1st width is disclosed as about 50-100 µm, which is squarely within the claimed range), and wherein the second width is less than the first width and ranges from 18 micrometers to 450 micrometers (2nd width 218 is disclosed as 30-80 µm in equation (2) in [0034], which is squarely within the claimed range. Note: the separately cited ranges each have a plurality of selectable values capable of meeting the claim. For example, selecting 64 µm for the 2nd width 218, and 84 µm for the 1st width meets the claim).
Illustrated below are marked and annotated figures of Figs. 2 and 3, and a marked and annotated enlarged portion of Fig. 3 of Lee.
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Regarding claim 10, Lee discloses the semiconductor structure of claim 9 (Fig. 3): wherein a first conductive bump opening of the first conductive bump openings (opening 214 of Opening Group 1, See annotated figure) is axially aligned with a first conductive bump opening of the second conductive bump openings (opening 210 of Opening Group 1, See annotated figure) to define a first opening (Opening Group 1) extending through the first dielectric material (completely vertically through) and through the second dielectric material (completely vertically through), and a first conductive bump (a respective 332) is arranged within the first opening; wherein a second conductive bump opening of the first conductive bump openings (opening 214 of Opening Group 2, See annotated figure) is axially aligned with a second conductive bump opening of the second conductive bump openings (opening 210 of Opening Group 2, See annotated figure) to define a second opening (Opening Group 2) extending through the first dielectric material (completely vertically through) and through the second dielectric material (completely vertically through), and a second conductive bump (a respective 332) is arranged within the second opening.
Regarding claim 11, Lee discloses the semiconductor structure of claim 10, wherein nearest outer sidewalls defined by the first and second openings (See enlarged portion of Fig. 3) are spaced apart only by the first dielectric material and the second dielectric material (there are no other materials or structures intervening).
Regarding claim 12, Lee discloses the semiconductor structure of claim 10 (Fig. 3, enlarged portion), wherein the first dielectric material extends from a first inner sidewall (See annotated figure) to a second inner sidewall (See annotated figure) along a lateral plane (See annotated figure for direction designation) without any conductive features intersecting the lateral plane (the cited portion of 206 has no structures included in it, conductive or otherwise), wherein the first inner sidewall is defined by the first conductive bump opening of the first conductive bump openings (the cited sidewall is the same sidewall disclosed for opening 214 of Opening Group 1) and the second inner sidewall is defined by the second conductive bump opening of the first conductive bump openings (the cited sidewall is the same sidewall disclosed for opening 214 of Opening Group 2).
Regarding claim 13, Lee discloses the semiconductor structure of claim 12 (Fig. 3), wherein the second dielectric material extends over the first dielectric material (directly over), and wherein outer edges of the first and second conductive bumps overlie (vertically overlie at least indirectly) outer edges of an upper surface of the second dielectric material.
Regarding claim 14, Lee discloses the semiconductor structure of claim 9, further comprising: a second substrate (102) including a second plurality of conductive pads (330) that are laterally spaced apart from one another on the second substrate, wherein the first plurality of conductive bumps couple (directly couple) the second plurality of conductive pads to the first plurality of conductive pads.
Regarding claim 15, Lee discloses the semiconductor structure of claim 14 (Fig. 3), wherein an upper surface of the multi-tiered solder-resist structure is spaced apart from a lower surface of the second substrate by a gap (See annotated figure), and further comprising: a molding material (336) disposed over the first substrate and filling the gap (completely filling).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claims 16-17 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Hu (US 20110056738 A1).
Regarding independent claim 16, Lee discloses a semiconductor structure (Fig. 3), comprising:
a first substrate (104) including a first plurality of conductive pads (217) that are laterally spaced apart from one another (See annotated figure for direction designation);
a first plurality of conductive bumps (332) disposed on the first plurality of conductive pads (directly on), respectively; and
a multi-tiered solder-resist structure (the collection of 206 with 208) comprising:
a first tier (206) comprising a first dielectric material ([0026]: “a non-conductive material”) and including first conductive bump openings (214) having a first opening width (216, See Fig. 2 for measurement markings) defined by inner sidewalls of the first tier (See annotated enlarged portion of Fig. 3), the first tier having a first width (left step width 329 of layer 206 + tier width 218 of layer 208 which vertically overlaps layer 206 + right step width 329 of layer 206, shorthand written as widths 329+218+329; See annotated figure for measurement annotations consistent with the top-down view of Fig. 2. Note: the width of 329 is disclosed as [0041]: “about 10 µm”; and width 218 is disclosed as 30-80 µm in equation (2) in [0034]. Thus, the first width is disclosed as 10 + 30 through 80 + about 10, or about 50-100 µm.) measured through the first dielectric material (as measured in the lateral direction) between the inner sidewalls of the first tier in a cross-sectional view (Fig. 3 is a cross-sectional view); and
a second tier (208) overlying the first tier (directly vertically overlying), the second tier comprising a second dielectric material ([0026]: “a non-conductive material”) and including second conductive bump openings (210) having a second opening width (212, See Fig. 2 for measurement markings) defined by inner vertical sidewalls of the second tier (See annotated enlarged portion of Fig. 3), the second tier having a second width (218, See Fig. 2 or annotated Fig. 3 for measurement markings) measured through the second dielectric material between the inner vertical sidewalls of the second tier in the cross-sectional view (Fig. 3 is a cross-sectional view);
wherein a conductive bump of the first plurality of conductive bumps has a downwardly-facing planar surface (a curved barrel-shaped surface of bump 332, See annotated Fig. 3) that extends at least partially over and interfaces with a top surface of the second tier (indirectly vertically over) so the downwardly-facing planar surface of the conductive bump is co-planar with the top surface of the second tier (coplanar at least at a point);
wherein the first opening width (opening 214 is disclosed having width 216 in equation (1) in [0030]: less than 60-80 µm) ranges from 20 micrometers to 500 micrometers (width 216 is squarely within this range), and wherein the second opening width (opening 210 is disclosed having width 212 in equation (1) in [0030]: greater than 80 µm) is greater than the first opening width (equation (1) in [0034] shows the “greater than” numerical relation) and ranges from 22 micrometers to 550 micrometers (width 212 is squarely within this range).
Lee teaches the conductive bump and the second tier, however fails to teach the claimed shape of the conductive bump: “wherein a conductive bump of the first plurality of conductive bumps has a downwardly-facing planar surface that extends at least partially over and interfaces with a top surface of the second tier so the downwardly-facing planar surface of the conductive bump is co-planar with the top surface of the second tier;” because Lee only teaches a curved shaped bump over a top surface of the second tier.
Hu discloses shapes of conductive bumps:
wherein a conductive bump (Fig. 4D: one of 34`) of the first plurality of conductive bumps (34`) has a downwardly-facing planar surface (See annotated figure) that extends at least partially over and interfaces with (directly interfaces) a top surface of the second tier (See annotated figure) so the downwardly-facing planar surface of the conductive bump is co-planar with the top surface of the second tier (coplanar at the direct interface);
Modifying the shape of the first plurality of conductive bumps (of Lee) by incorporating the shape disclosed by Hu (Hu: Fig. 4D) would arrive at the claimed bump shape configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Hu teaches this shape is included in a finite selection of known suitable shapes (Hu: Fig. 4D and 5B) useful for the same purpose (bumps 34`/51,`contained by first and second tiers 31), and this finite selection overlaps in scope with the bump shape disclosed by Lee (Hu: Fig. 5B overlaps in scope with Lee: Fig. 3). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different bump shape. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
Illustrated below is a marked and annotated figure of Fig. 4D and Fig. 5B of Hu.
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Regarding claim 17, Lee in view of Hu discloses the semiconductor structure of claim 16 (Lee: Fig. 3), further comprising:
a second substrate (102) including a second plurality of conductive pads (330) that are laterally spaced apart from one another on the second substrate, wherein the first plurality of conductive bumps couple (directly couple) the second plurality of conductive pads to the first plurality of conductive pads;
wherein the conductive bump contacts (directly contacts) a conductive pad of the second plurality of conductive pads (one pad 330), wherein the conductive pad comprises an outer sidewall facing a first direction (one lateral direction, See annotated figure for “lateral” direction designation), wherein an upper segment of an outer sidewall of the conductive bump is laterally offset (the rounded shape described further below contains a plurality of lateral distances when measured at different places on the bump, thus at least some amount of “offset” is possessed by this structure) from the outer sidewall of the conductive pad by a first distance in the first direction (See annotated figure for “upper” direction. The upper portion of bumps 332 are rounded in Lee: Fig. 3, and this shape is retained with the modified shape disclosed by Hu: Fig. 4D, which also shows a similar rounded shape.), wherein the downwardly-facing planar surface interfaces with the top surface of the second tier along a second distance (the lateral “distance” of the interface) that is greater than the first distance (“greater” because the rounded shape of Hu has at least some of the planar surface laterally outward from at least some portion of the rounded surface, and therefore “greater”).
Regarding claim 22, Lee in view of Hu discloses the semiconductor structure of claim 16 (Lee: Fig. 3), wherein the second width is measured along a lateral plane (a lateral direction was already designated in the claim 16 rejection), and wherein the conductive bump has a bump width (See annotated figure) as measured between outermost sidewalls of the conductive bump along the lateral plane (Bump 332 within opening 210 has a width matching width 212 of opening 210; this width is disclosed as greater than 80 µm in equation (1) in [0030]. Additionally, bump 332 has a barrel portion vertically above opening 210 wider than width 212. Thus bump 332 has a width wider than 80 µm), wherein the bump width is greater than the second width (the bump width is cited as greater than 80 µm, which is greater than the second width cited as 30-80 µm).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee and Hu as applied to claim 17 above, and further in view of Huang (US 20190067231 A1).
Regarding claim 18, Lee in view of Hu discloses the semiconductor structure of claim 17, but fails to teach “a first die disposed over a first portion of the second substrate and connected to the second substrate through a first plurality of microbumps; and a second die disposed over a second portion of the second substrate and connected to the second substrate through a second plurality of microbumps”.
Huang discloses a second substrate (Fig. 9A: 82), and further discloses the second substrate configuration may be varied to include a plurality of configurations (the embodiments of Fig. 9A and Fig. 8, selecting the embodiment of Fig. 9A), including: a first die (84 on left, See annotated figure) disposed over a first portion of the second substrate (See annotated figure) and connected to the second substrate through a first plurality of microbumps (respective 85); and a second die disposed (84 on right, See annotated figure) over a second portion of the second substrate (See annotated figure) and connected to the second substrate through a second plurality of microbumps (respective 85).
Lee (in view of Hu) and Huang separately disclose each element claimed. One of ordinary skill in the art before the effective filing date could have combined the varied second substrate configuration of Huang with the second/first substrate configuration of Lee in view of Hu, and in combination each element merely performs the same function as it does separately (i.e. the second substrate performing the function of an integrated circuit). One of ordinary skill in the art before the effective filing date would have recognized that the results of the combination were predictable because: Huang teaches the second substrate performing the function of an integrated circuit (Huang: [0039]: “package… interposer… semiconductor dies”); and because Lee (in view of Hu) teaches configuration of the second substrate may be varied by disclosing a plurality of second substrate species configurations ([0025]: “a flip chip or an integrated circuit die”). One of ordinary skill in the art before the effective filing date would have been motivated to do so to produce a semiconductor structure having alternative functional utility, by the inclusion of additional components, i.e., a first and second die. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because it is a mere combination of prior art elements according to known second substrate configurations yielding a predictable semiconductor structure. MPEP 2143 (I)(A).
Regarding claim 19, Lee in view of Hu and Huang discloses the semiconductor structure of claim 18 (Lee: Fig. 3), wherein an upper surface of the multi-tiered solder-resist structure is spaced apart from a lower surface of the second substrate by a gap (See annotated figure), and further comprising: a molding material (336) disposed over the first substrate and filling the gap (completely filling).
Allowable Subject Matter
Claims 1-7 and 23 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 1-7 and 23 is the inclusion of the limitation “wherein the first conductive bump has a planar surface interfacing with a top surface of the second tier along a first distance and a second outermost sidewall over the top surface of the second tier, wherein the second outermost sidewall is laterally offset from a first inner vertical sidewall of the inner vertical sidewalls by a second distance less than the first distance” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “distance”, “offset”, and “less than” in combination with all other limitations in claim 1. The claim is now directed to a particular eccentric arrangement of structures, which differs from the concentric arrangements found in the cited prior art. This eccentric arrangement was not found or rendered obvious by looking elsewhere in the prior art.
Response to Arguments
Applicant's arguments filed 6/29/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 9 that “the contact pad 217 of Lee is analogous to the claimed first plurality of conductive bumps, and the first resist layer 206 of Lee is analogous to the claimed first tier. (See GA of 02/19/26, pp. 3-4). The annotated version of Fig. 3 of Lee shows that a top surface of the contact pad 217 is spaced above (e.g., not coplanar) a surface of the carrier 104 (e.g., the top surface of the carrier 104).”. Remarks at pg. 10.
Examiner’s reply:
The examiner does not find Applicant’s remarks persuasive because “the contact pad 217 of Lee is analogous to the claimed first plurality of conductive bumps […] Thus, Lee does not teach or suggest the first plurality of conductive bumps having a top surface coplanar to a surface of the first substrate” is not how the reference is mapped to the claims. Rather, the pads Lee: 217 are mapped to the claimed “a first plurality of conductive pads” and bumps Lee: 206 are mapped to the claimed “a first plurality of conductive bumps”. Accordingly, Applicant’s remarks are directed to a configuration of features different from the claim. The examiner is interpreting the claimed “a first substrate” as a collection of structures including the claimed “a multi-tiered solder-resist structure”. This interpretation renders the claim definite and supported by the original disclosure. Additionally, the examiner finds “top” as claimed reasonably including a plurality of surfaces beyond the configurations explicitly disclosed by Applicant (MPEP 2111). For example, “top” as claimed could reasonably include a surface a top portion of the bump. The examiner notes this interpretation is consistent with the interpretation of these terms required to render the instant claims definite and supported by the original disclosure. Accordingly, the claim is rejected in substantially the same way as before, with additional citations and remarks added as necessitated by claim amendment and to promote clarity of the record.
Note: The examiner believes Applicant intended to include the new limitation with the “first plurality of conductive pads” in claim 9, line 2, not the “first plurality of conductive bumps” in claim 9, line 4. Nevertheless, no changes have been made to the claim language for the instant Office action and the claim has been examined as presented in the instant set of claims.
Applicant argues:
Applicant argues with respect to amended claim 9 that “Further, a planar bottom surface of the first resist layer 206 is spaced below (e.g., not coplanar) the top surface of the contact pad 217. […], and the first tier having a planar bottom surface that is coplanar to the top sur face of the first plurality of conductive pads and that is coplanar to the surface of the first substrate, as recited in amended claim 9”. Remarks at pg. 10.
Examiner’s reply:
The examiner does not find Applicant’s remarks persuasive because “bottom” as claimed reasonably including a plurality of surfaces beyond the configurations explicitly disclosed by Applicant (MPEP 2111). For example, “bottom” as claimed could reasonably include a downward facing surface at any particular level relative to the substrate. Additionally, “planar” as claimed could reasonably include a multi-faceted surface where each facet facing downward is flat, as is shown in the cited portions of the prior art. Furthermore, line 2 of the claim requires the substrate to include the pads, and thus, the claim as written reasonably encompasses any surface of the pads also being a surface of the substrate. Accordingly, the claim is rejected in substantially the same way as before, with additional citations and remarks added as necessitated by the claim amendments and to promote clarity of the record.
Applicant argues:
Applicant argues with respect to amended claim 16 that “Claim 16 recites, in part, a conductive bump of the first plurality of conductive bumps has a downwardly-facing planar surface that extends at least partially over and interfaces with a top surface of the second tier so the downwardly-facing planar surface of the conductive bump is co-planar with the top surface of the second tier.”. Remarks at pg. 11.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Hu is relied upon in the instant Office action to teach the contended features, as necessitated by the claim amendment.
Applicant argues:
Applicant argues with respect to amended claim 1 that “Thus, the cited art, considered individually and/or in combination fails to teach or suggest the first conductive bump has a planar surface interfacing with a top surface of the second tier along a first distance and a second outermost sidewall over the top surface of the second tier, wherein the second outermost sidewall is laterally offset from a first inner vertical sidewall of the inner vertical sidewalls by a second distance less than the first distance”. Remarks at pg. 14.
Examiner’s reply:
Applicant’s arguments, see pg. 14, filed 6/29/2026, with respect to the newly added limitation have been fully considered and are persuasive. The rejection of claim 1 has been withdrawn.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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