Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/604,947 filed on 03/14/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant’s election with traverse of Species I in the reply filed on 05/19/2026 is acknowledged. Upon reconsideration of Applicant’s traversal and the pending claims, the traversal is persuasive. The prior restriction requirement is hereby withdrawn, and Species I and II are rejoined and examined on the merits in the present Office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub # 2018/0323187 to Moen et al. (Moen).
Regarding independent claim 1, Moen discloses a structure (Fig. 3A) comprising:
a semiconductor body (upper body of 315 through which 352 is extended, see Examiner’s Mark-up below); and
an isolation structure including:
a trench isolation region (Fig. 3A: 352) extending through the semiconductor body (upper body of 315) to an insulator layer (361 or 362 is considered to be an insulator layer), wherein the trench isolation region (352) has a first edge (see Examiner’s Mark-up below) and a second edge (see Examiner’s Mark-up below) opposite the first edge; and
isolating first transistors (Fig. 3A: 311-314) connected in series (¶0042) on a first portion of the semiconductor body (upper body of 315) adjacent to the first edge, wherein the isolating first transistors (311-314) are connected to receive a supply voltage to maintain the isolating first transistors an off state (this limitation “to receive a supply voltage to maintain the isolating first transistors an off state” pertains to an intended function of the claimed device structure. It is noted that the prior art teaches the same device structure claimed, and therefore, the device of the prior art is capable of performing the same function of maintaining the device in an off state when the transistors 311-314 receive a supply voltage. More specifically when transistors 311-314 receives a supply voltage that is lower than the threshold voltage of the transistors 311-314 then transistors 311-314 will remain or maintain in off state.
The claim does not specify any particular supply voltage that would distinguish over any voltage that can be applied to the prior art transistors that is lower than the threshold voltage of the transistors 311-314. Therefore, the prior art device is capable of performing the same function as claimed).
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Regarding claim 8, Moen discloses a semiconductor substrate (entire 301considered to be a semiconductor substrate) and a well region (Fig. 3A: 554) in the semiconductor substrate below the isolation structure (352).
Regarding claim 9, Moen discloses wherein the well region (Fig. 3A: 554) is a P-type well region (¶0043).
Regarding claim 10, Moen discloses a well tap (Fig. 3A: 573 is presently considered to be a well tap because it can receive voltage) immediately adjacent to the well region (554), wherein the well tap (573) is connected to receive a back gate bias voltage. One of ordinary skill in the art would understand that the well tap electrically biases the well region and therefore receives a back gate bias voltage, as the well potential constitutes the body/back gate bias for transistors formed in the well. Furthermore, in MOS technology, the purpose of a well tap is to bias the body (substrate/well) of the transistor to control the body potential and avoid floating body effects.
Claim 11 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pat # 9,437,681 to Lee et al. (Lee).
Regarding independent claim 11, Lee discloses a structure (Fig. 2) comprising:
a semiconductor body (Fig. 2: 201); and
an isolation structure including:
a trench isolation region (Fig. 2: 400) extending through the semiconductor body (201) to an insulator layer (410), wherein the trench isolation region (400) has a first edge (see Examiner’s Mark-up below) and a second edge (see Examiner’s Mark-up below) opposite the first edge; and
isolating first transistors (Fig. 2: 200) connected in series (col. 7, lines 28-30) on a first portion of the semiconductor body (201) adjacent to the first edge, wherein the isolating first transistors are P-channel field effect transistors (col. 7, lines 28-30), wherein each isolating first transistor (200) has a first source region (202) and a first gate (203) connected to a corresponding first bias voltage node to receive a first positive supply voltage to maintain the isolating first transistors in an off state.
It is noted that the limitation “connected to a corresponding first bias voltage node to receive a first positive supply voltage to maintain the isolating first transistor in an off state” describes the functional operation of the claimed PMOS isolation transistor structure rather than imposing additional structural distinctions over the prior art structure disclosed by Lee.
Lee discloses substantially the same PMOS isolation transistor structure (200), including PMOS transistors connected in series adjacent to the trench isolation region. One of ordinary skill in the art would recognize that PMOS isolation transistors are maintained in a nonconductive state by applying a sufficiently positive gate bias relative to the source potential. Accordingly, the PMOS isolation transistors of Lee are necessarily capable of being maintained in an OFF state by application of a positive supply voltage to the gate bias node.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 12-13 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over US Pat # 9,437,681 to Lee et al. (Lee) in view of US Pub # 2018/0323187 to Moen et al. (Moen).
Regarding claim 12, Lee discloses all of the limitations of claim 11 from which this claim depends.
Lee fails to explicitly disclose a functional first transistor on the semiconductor body and separated from the first edge by the first portion.
Moen discloses a functional first transistor (Fig. 3A: any of 311-314) on the semiconductor body (upper portion of 315) and separated from the first edge by the first portion (see Examiner’s Mark- up below).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the first portion of the semiconductor body of Lee with the functional first transistor as taught by Moen so as to form an RF switch (¶0042).
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Regarding claim 13, Lee as previously modified discloses all of the limitations of claim 12 from which this claim depends.
Lee further teaches a first drain region (Fig. 2: 202) of the isolating first transistor (200) in the first portion of the semiconductor body distal to the first edge.
Moen teaches a functional first transistor (see the rejection of claim 12) coupled to the first drain region (as taught by Lee and Moen). The combined structure therefore teaches the claimed connection between the functional transistor and the first drain region.
The recitation that the first drain region is connectable by the functional first transistor “to receive a first data signal with a first maximum voltage no greater than the first positive supply voltage” pertains to the functional operation and intended use of the claimed structure rather than imposing additional structural limitations.
The combined structure of Lee and Moen is necessarily capable of receiving a data signal having a maximum voltage not exceeding the positive supply voltage, since no additional structure is recited for generating, enforcing, or limiting the signal voltage. The voltage level of the received data signal is determined by the operating conditions and the external signal source rather than by any structural distinction of the claimed device.
Regarding claim 17, Lee as previously modified discloses all of the limitations of claim 11 from which this claim depends. Lee discloses a semiconductor substrate (Fig. 2: 100 and col. 6, lines 62-64).
Lee fails to explicitly disclose a well region in the semiconductor substrate below the isolation structure.
Moen discloses a well region (Fig. 3A: 554) in the semiconductor substrate (301) below the isolation structure (352).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the semiconductor substrate of Lee with a well region as taught by Moen so as to provide a relatively high resistance path near the upper surface of the substrate in the isolation region (¶0047).
Regarding claim 18, Lee as previously modified discloses all of the limitations of claim 17 from which this claim depends.
Lee fails to explicitly disclose wherein the well region is a P-type well region.
Moen discloses wherein the well region (Fig. 3A: 554) is a P-type well region (¶0043).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the semiconductor substrate of Lee with a well region as taught by Moen so as to provide a relatively high resistance path near the upper surface of the substrate in the isolation region (¶0047).
Regarding claim 19, Lee as previously modified discloses all of the limitations of claim 17 from which this claim depends.
Lee fails to explicitly disclose a well tap immediately adjacent to the well region, wherein the well tap is connected to receive a back gate bias voltage.
Moen discloses a well tap (Fig. 3A: 573 is presently considered to be a well tap because it can receive voltage) immediately adjacent to the well region (554), wherein the well tap (573) is connected to receive a back gate bias voltage. One of ordinary skill in the art would understand that the well tap electrically biases the well region and therefore receives a back gate bias voltage, as the well potential constitutes the body/back gate bias for transistors formed in the well. Furthermore, in MOS technology, the purpose of a well tap is to bias the body (substrate/well) of the transistor to control the body potential and avoid floating body effects.
Allowable Subject Matter
Claim 20 is allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claim 20, the prior art of record fails to teach or render obvious the combination of limitations of the independent claim 20 “isolating first P-type field effect transistors (PFETs) connected in series on a first portion of the semiconductor body adjacent to the first edge, wherein at least a first source region in the first portion proximal to the first edge and first gates of the isolating first PFETs are connected to at least one first bias voltage node and wherein the at least one first bias voltage node is connected to receive a first positive supply voltage to maintain the isolating first PFETs in an off state; and isolating second PFETs connected in series on a second portion of the semiconductor body adjacent to the second edge, wherein at least a second source region in the second portion proximal to the second edge and second gates of the isolating second PFETs are connected to at least one second bias voltage node, wherein the at least one second bias voltage node is connected to receive a second positive supply voltage to maintain the isolating second PFETs in the off state, and wherein the second positive supply voltage is different from the first positive supply voltage” taken in combination with all other limitations of independent claim 20.
Claims 2-7 and 14-16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 recites:
“wherein the isolating first transistors are P-channel field effect transistors, wherein the structure further includes a first bias voltage node electrically connected to a first source region in the first portion of the semiconductor body proximal to the first edge and first gates of the isolating first transistors, and wherein the first bias voltage node is connected to receive a first positive supply voltage to maintain the isolating first transistors in the off state.”
Claim 14 recites:
“wherein the isolation structure further includes isolating second transistors connected in series on a second portion of the semiconductor body adjacent to the second edge, wherein the isolating second transistors are P-channel field effect transistors, wherein each isolating second transistor has a second source region and a second gate connected to a corresponding second bias voltage node to receive a second positive supply voltage to maintain the isolating second transistors in the off state, and wherein the second positive supply voltage is different from the first positive supply voltage.”
The considered prior art of record appears to fail to teach or render obvious the instant limitation in combination with all of the limitations of the independent claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Nagasato et al. (US Pat # 9,666,580), Agrawal (US Pat # 9,385,708), Kumar (US Pub # 2015/0263707), Mallikarjunaswamy (US Pat # 8,174,070), Itoh et al. (US Pat # 7,759,714), Yang (U.S. Pat # 7,535,057), Rao et al. (U.S. Pat# 6,522,582), Srinivasan et al. (U.S. Pat # 6,294,817) and Davis et al. (U.S. Pat # 5,892,264).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHSEN AHMADI whose telephone number is (571)272-5062. The examiner can normally be reached M-F: 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHSEN AHMADI/ Primary Examiner, Art Unit 2896
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