DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 16-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 16 states “a polymer over the solder resist” however, the specification provides no support for this limitation. The Specification only teaches that the solder resist may be formed of a polymer (paragraph [0015]). There are no other instances in the specification of the term “polymer” besides that which is found in paragraph [0015]. Claims 17-20 are rejected thusly as they do not provide any additional clarity or clarification to the claim that would overcome the rejection of the independent claim 16 to which they depend.
Claims 5 and 6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The features “signal line” “power line” “ground line” and “dummy conductive line” are not found in the specification. Power, signal and ground are referred in conjunction with certain layers (see [0014], and dummy is referred to in conjunction with the term features (see [0014][0017]). Claims should be drawn using the language as written in the specification in order to comply with the statutory written description requirement.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 10, 13 and 14 of U.S. Patent No. 11,037,852 (‘852). Although the claims at issue are not identical, they are not patentably distinct from each other because they overlap in scope.
Pertaining to claim 1: A package comprising: Claim 10 line 1 (‘852)
a die stack directly bonded to a conductive layer in a package substrate; Claim 10 lines 2-5 (‘852)
a solder resist covering a first portion of the conductive layer; Claim 10 lines 6-9 (‘852) note that the solder resist as claimed is placed to “cover” a portion of the conductive layer even if that term is not explicitly used
a thermal interface material extending through the solder resist to physically contact an electrically conductive material of the conductive layer; and Claim 10 lines 6-9 (‘852)
a heat dissipation feature surrounding the die stack and thermally connected to the thermal interface material. Claim 10 line 10 (note “surrounding” is broad and in the broadest sense the placement as claimed in the ‘852 patent would encompass “surrounding” the die stack.)
See Col 10 lines 30-40 (claim 10 below) of the cited patent (‘852) which overlaps in scope with the claimed invention
Pertaining to claim 2: See claim 13 (‘852) and note that the claims don’t exclude intervening layers with respect to adhering elements to one another.
Pertaining to claim 3: See claim 14 (‘852)
Claims 1-3, 5-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5 and 6 of U.S. Patent No. 10,461,009 (‘009). Although the claims at issue are not identical, they are not patentably distinct from each other because they overlap in scope.
Pertaining to claim 1: A package comprising: Claim 1 line 1 (‘009)
a die stack directly bonded to a conductive layer in a package substrate; Claim 1 lines 2-10 (‘009)
a solder resist covering a first portion of the conductive layer; Claim 1 lines 11-13 (‘009)
a thermal interface material extending through the solder resist to physically contact an electrically conductive material of the conductive layer; Claim 1 line 13 (‘009) and
a heat dissipation feature surrounding the die stack and thermally connected to the thermal interface material. Claim 2 lines 1-3 (‘009)
Pertaining to claim 2: See claim 2 (‘009)
Pertaining to claim 3: See claim 3 (‘009)
Pertaining to claim 5: See claim 5 (‘009)
Pertaining to claim 6: See claim 6 (‘009)
Pertaining to claim 7, selecting the dies to be memory dies, as opposed to any other type of functional element, would have been obvious to one of ordinary skill in the art at the time the invention was filed. When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. (‘009) above (see rejection of claim 1 above) and further in view of Chiu US 2005/0245060. Chiu teaches a thermally conductive lid 130 over a die stack 20. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to add a thermally conductive lid such as that taught by Chiu to a die stack for the purpose of dissipating heat and preventing damage.
Claims 10 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 9,735,082 (‘082). Although the claims at issue are not identical, they are not patentably distinct from each other because they overlap in scope.
Pertaining to claim 10. A package comprising:
a die stack; “a die stack” claim 1 line 4 (‘082)
a package substrate, wherein the die stack is electrically and physically connected to a conductive feature in the package substrate; “a package comprising…a substrate comprising a conductive layer…a die stack…electrically connected to the conductive layer” claim 1 lines 1-4 (‘082)
a first thermal interface material (TIM) (high thermal conductivity material of claim 1) (‘082) extending through a solder resist (see claim 2) to the conductive feature, wherein the die stack and the first TIM each overlap the conductive feature See claim 2 (‘082), the solder resist doesn’t cover a portion of the conductive layer, thus the die stack and the first TIM (thermal conductivity material) would be in the opening ie extending through;
a heat dissipation ring thermally connected to the die stack through the first TIM, wherein the heat dissipation ring surrounds the die stack in a top down view “a contour ring” see claim 1 and additionally see claim 5 which implies the structure “past sidewalls of the substrate”; and
a heat dissipation lid over and thermally connected to the die stack see claim 3 (‘082).
Allowable Subject Matter
Claims 4, 9, 11-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertaining to claim 4, the prior art does not teach nor suggest in combination with claims 1 and 2, wherein the adhesive material is disposed on a first side of the thermal interface material and a second side of the thermal interface material, and the first side of the thermal interface material is opposite to the second side of the thermal interface material.
Pertaining to claim 9, the prior art does not teach nor suggest in combination with claim 1, further comprising a passive device on the package substrate, wherein the die stack and the passive device each overlap the conductive layer.
Pertaining to claim 11, the prior art does not teach nor suggest in combination with claim 10, wherein the heat dissipation lid is attached to a top surface of the die stack by a second TIM.
Pertaining to claim 13, the prior art does not teach nor suggest in combination with claim 10, wherein the heat dissipation ring is adhered to a top surface of the solder resist by a second adhesive, and wherein the first TIM extends through the second adhesive.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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