DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 11 and 16 - 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (U.S. Patent Publication No. 2022/0310411).
Regarding claim 1, in Figure 9, Chen discloses an electronic device, comprising: a flexible circuit structure (600, paragraph [0031]); a package structure (PU) supported by the flexible circuit structure and comprising a first stress-dissipating part (35) at a periphery region of the package structure; and a flexible encapsulation layer (402) encapsulating the package structure.
Regarding claim 2, Chen discloses wherein the package structure comprises a central region, and wherein a first distance between the central region and the flexible circuit structure is shorter than a second distance between the first stress-dissipating part and the flexible circuit structure (Figure 9).
Regarding claim 3, Chen discloses wherein the first stress-dissipating part comprises a beveled edge in a cross-sectional view (Figure 9).
Regarding claim 4, Chen discloses wherein the first stress-dissipating part has a stepped structure tapering toward the flexible circuit structure (Figure 9).
Regarding claim 5, Chen discloses wherein the package structure further comprises a substrate defining the first stress-dissipating part, a first region connected a connection element, and a second region extending from the first stress-dissipating part to the first region, and wherein a first length of the first stress-dissipating part projecting on the flexible circuit structure is greater than a second length of the second region projecting on the flexible circuit structure (Figure 9).
Regarding claim 6, Chen discloses wherein the package structure comprises an encapsulation layer defining the first stress-dissipating part and a first electronic component encapsulated by the encapsulation layer (Figure 9).
Regarding claim 7, Chen discloses wherein the package structure comprises a substrate disposed between the encapsulation layer and the flexible circuit structure, and wherein the substrate and the encapsulation layer collectively define the first stress-dissipating part (Figure 9).
Regarding claim 8, Chen discloses wherein the package structure further comprises a substrate disposed over the encapsulation layer and a second electronic component disposed over the substrate (Figure 9).
Regarding claim 9, Chen discloses wherein the package structure further comprises a second stress-dissipating part at the periphery region of the package structure, and wherein the second stress-dissipating part is geometric distinct from the first stress-dissipating part (Figure 9).
Regarding claim 10, Chen discloses wherein, in a bottom view, the first stress-dissipating part has a first edge and a second edge spaced apart from the first edge, and the first edge is non-parallel with the second edge (Figure 9).
Regarding claim 11, Chen discloses wherein, in the bottom view, the flexible circuit structure has a lateral edge substantially parallel with the second edge (Figure 9).
Regarding claim 16, in Figure 9, Chen discloses an electronic device, comprising: a circuit structure (600, paragraph [0031]); and a package structure (PU) disposed above the circuit structure and comprising a first periphery portion (35) configured to dissipate stress between the package structure and the circuit structure.
Regarding claim 17, Chen discloses wherein the first periphery portion has a surface non-parallel to an upper surface of the circuit structure and non-perpendicular to a lateral surface of the package structure (Figure 9).
Regarding claim 18, Chen discloses wherein the package structure comprises a second periphery portion opposite to the first periphery portion and configured to dissipate stress between the package structure and the circuit structure (Figure 9).
Regarding claim 19, Chen discloses wherein the second periphery portion is asymmetrical to the first periphery portion with respect to a central line of the package structure (Figure 9).
Regarding claim 20, Chen discloses an encapsulation layer encapsulating the package structure and disposed between the package structure and the circuit structure (Figure 9).
2. Claims 12 - 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al. (U.S. Patent Publication No. 2018/0358304).
Regarding claim 12, in Figure 2B (see Annotated Figure 2B below) Hsu discloses an electronic device, comprising: a first region (left side region); a second region (right side region) distant from the first region; and a package structure (comprising 12, 20, 16) located in a third region (middle region) between the first region and the second region, wherein the package structure is configured to allow the first region and the second region bending toward the package structure in different extents (Figure 2B).
PNG
media_image1.png
230
436
media_image1.png
Greyscale
Regarding claim 13, Hsu discloses wherein the package structure comprises a first edge proximate to the first region and a second edge proximate to the second region, and a first dimension of the first edge is different from a second dimension of the second edge (Figure 2B).
Regarding claim 14, Hsu discloses wherein the package structure comprises a first edge proximate to the first region and a second edge proximate to the second region, and the package structure has a bottom surface, and wherein a first angle defined by the first edge and the bottom surface is different from a second angle defined by the second edge and the bottom surface (Figure 2B).
Regarding claim 15, Hsu discloses a circuit structure disposed under the package structure, wherein the package structure comprises a first edge proximate to the first region and a second edge proximate to the second region, and a first length of the first edge projecting on the circuit structure is different from a second length of the second edge projecting on the circuit structure (Figure 2B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847