Prosecution Insights
Last updated: August 17, 2026
Application No. 18/605,706

ELECTRONIC DEVICE

Final Rejection §103
Filed
Mar 14, 2024
Examiner
BURNS, TREMESHA WILLIS
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Semiconductor Engineering Inc.
OA Round
2 (Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
695 granted / 890 resolved
+10.1% vs TC avg
Strong +17% interview lift
Without
With
+17.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
49 currently pending
Career history
936
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
33.7%
-6.3% vs TC avg
§102
46.2%
+6.2% vs TC avg
§112
18.4%
-21.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 890 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant's arguments with respect to claims 1 – 20 have been considered but are moot in view of the new ground(s) of rejection. Claim Objections Claims 6, 8, 14, 15, 19, and 20 are objected to because of the following informalities: On line 6 of claim 6, the word first is misspelled as “firs.” On line 1 of claim 8, the phrase “the acute angle is range” should be “the acute angle is in a range.” Appropriate correction is required. On line 5 of claim 14, “smaller from” should be “smaller than.” On line 5 of claim 15, “smaller from” should be “smaller than.” On line 6 of claim 19, “smaller from” should be “smaller than.” On line 8 of claim 20, the word first is misspelled as “firs.” Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Low et al. (U.S. Patent Publication No. 2025/0126716). Regarding claim 1, in Figure 18, Low discloses an electronic device, comprising: a flexible circuit structure (201); a package structure (comprising 180, 822) supported by the flexible circuit structure and comprising a first stress-dissipating part (180) at a periphery region of the package structure; and a flexible encapsulation layer (1802) encapsulating the package structure, wherein the first stress-dissipating part comprises a first bevel edge (see annotated Figure 18 below) of a substrate of the package structure and a second bevel edge (see annotated Figure 18 below) of a second encapsulation layer of the package structure, wherein the first bevel edge and the second bevel edge collectively comprise a continuous slanted surface covered by the flexible encapsulation layer (see annotated Figure 18 below), wherein the continuous slanted surface intersects and is non-parallel to an interface between the substrate and the second encapsulation layer (see annotated Figure 18 below). Low does not specifically disclose module substrate 201 and film/layer 1802 as being flexible. However, providing a circuit/module structure and layers therein to be flexible is common place and well known in the art, and is merely a design option for a skilled artisan without the exercise of inventive skill. PNG media_image1.png 337 473 media_image1.png Greyscale Regarding claim 2, Low discloses wherein a first angle defined by the first bevel edge and the interface and a second angle defined by the second bevel edge and the interface are supplementary angles (Figure 18). Regarding claim 3, Low discloses an array of connection elements disposed between the flexible circuit structure and the package structure, wherein, in a bottom view, the array comprises a plurality of rows and a plurality of columns, each of which is non-parallel to a lateral surface of the flexible circuit structure (Figure 18). Regarding claim 4, Low discloses wherein in macroscopic scale, the first stress-dissipating part has a smooth tapering profile, and, in microscopic scale, the first stress-dissipating part has a stepped structure tapering toward the flexible circuit structure (Figure 18). Regarding claim 5, Low discloses wherein a first length of the first bevel edge projecting on the flexible circuit structure is greater than a second length of the second bevel edge projecting on the flexible circuit structure (Figure 18). Regarding claim 6, Low discloses wherein the package structure comprises a second stress-dissipating part asymmetrical to the first stress-dissipating part with respect to a central line of the package structure, and wherein when the electronic device is under a twisting test at a twisting angle in a range from 30º to 60º, a first portion of the flexible circuit structure proximate to the firs stress-dissipating part has a first curvature and a second portion of the flexible circuit structure proximate to the second stress-dissipating part has a second curvature smaller than the first curvature (Figure 18). Regarding claim 7, Low discloses wherein, in the bottom view, the array of connection elements is oriented at an acute angle relative to the flexible circuit structure (Figure 18). Regarding claim 8, Low discloses wherein the acute angle is range from 30º to 60º (Figure 18). Regarding claim 9, Low discloses wherein the package structure further comprises a second stress-dissipating part at the periphery region of the package structure, and wherein the second stress-dissipating part is geometric distinct from the first stress-dissipating part, wherein the second stress-dissipating part comprises a third bevel edge of the substrate and a fourth bevel edge of the second encapsulation layer, wherein the third bevel edge and the fourth bevel edge collectively comprise a second continuous slanted surface covered by the flexible encapsulation layer, wherein the second continuous slanted surface intersects and is non-parallel to the interface (Figure 18). Regarding claim 10, Low discloses wherein, in a bottom view, the first stress-dissipating part has a first side and a second side spaced apart from the first side, and the first side is non-parallel with the second side and a width of a projection of the first stress-dissipating part on the flexible circuit structure varies along a longitudinal direction (Figure 18). Regarding claim 11, Low discloses wherein the width of the projection of the first stress-dissipating part is greater at a first end adjacent to a first portion of the flexible circuit structure than a second end adjacent to a second portion of the flexible circuit structure, and wherein the second portion does not experience as much twisting as the first portion during a twisting test (Figure 18). Regarding claim 12, in Figure 18 (see Annotated Figure 18 below) Low discloses an electronic device, comprising: a first region (left side region); a second region (right side region) distant from the first region; a package structure (comprising 180, 822) located in a third region (middle region) between the first region and the second region; and a flexible encapsulation layer (1802) encapsulating the package structure, wherein the package structure comprises a plurality of stress-dissipating parts (180) configured to allow the first region and the second region bending toward the package structure in different extents (bending at the right and left divots 943), and wherein each of the first stress-dissipating parts comprises a first bevel edge (see annotated Figure 18 below) of a substrate of the package structure and a second bevel edge (see annotated Figure 18 below) of a second encapsulation layer (822) of the package structure, wherein the first bevel edge and the second bevel edge collectively comprise a continuous slanted surface covered by the flexible encapsulation layer (see annotated Figure 18 below), wherein the continuous slanted surface intersects and is non-parallel to an interface between the substrate and the second encapsulation layer (see annotated Figure 18 below). Low does not specifically disclose film/layer 1802 as being flexible. However, providing layers within a circuit/module structure to be flexible is common place and well known in the art, and is merely a design option for a skilled artisan without the exercise of inventive skill. PNG media_image2.png 337 473 media_image2.png Greyscale Regarding claim 13, Low discloses wherein the stress-dissipating parts comprises a first stress-dissipating part proximate to the first region and a second stress-dissipating part proximate to the second region, and a first dimension of the first stress-dissipating part is different from a second dimension of the second stress-dissipating part (Figure 18). Regarding claim 14, Low discloses wherein the package structure comprises a third bevel edge of the substrate proximate to the second region, wherein the first bevel edge of the substrate is proximate to the first region, and the package structure has a bottom surface, and wherein a first angle defined by the first bevel edge and the bottom surface is smaller from a second angle defined by the third bevel edge and the bottom surface, such that the first region is allowed to be bent in a greater extent than the second region (Figure 18). Regarding claim 15, Low discloses a circuit structure disposed under the package structure, wherein the stress-dissipating part comprises a first stress-dissipating part proximate to the first region and a second stress-dissipating part proximate to the second region, and a first length of the first stress-dissipating part projecting on the circuit structure is greater from a second length of the second stress-dissipating part projecting on the circuit structure, such that the first region is allowed to be twisted in a greater extent than the second region (Figure 18). Regarding claim 16, in Figure 18, Low discloses a electronic device, comprising: a circuit structure (201); a package structure (comprising 180, 822) disposed above the circuit structure and comprising a first periphery portion (180) configured to dissipate stress between the package structure and the circuit structure; and a flexible encapsulation layer (1802) encapsulating the package structure, wherein the first periphery portion comprises a first bevel edge (see annotated Figure 18 above) of a substrate of the package structure and a second bevel edge (see annotated Figure 18 above) of a second encapsulation layer of the package structure, wherein the first bevel edge and the second bevel edge collectively comprise a continuous slanted surface covered by the flexible encapsulation layer (see annotated Figure 18 above), wherein the continuous slanted surface intersects and is non-parallel to an interface between the substrate and the second encapsulation layer (see annotated Figure 18 above). Low does not specifically disclose film/layer 1802 as being flexible. However, providing layers within a circuit/module structure to be flexible is common place and well known in the art, and is merely a design option for a skilled artisan without the exercise of inventive skill. Regarding claim 17, Low discloses wherein, in a bottom view, the first periphery portion has a first side and a second side spaced apart from the first side, and the first side is non-parallel with the second side and a width of a projection of the first periphery portion on the flexible circuit structure varies along a longitudinal direction (Figure 18). Regarding claim 18, Low discloses wherein the width of the projection of the first periphery portion is greater at a first end adjacent to a first portion of the flexible circuit structure than a second end adjacent to a second portion of the flexible circuit structure, and wherein the first portion experience greater twisting than the second portion during a twisting test (Figure 18). Regarding claim 19, Low discloses wherein the package structure comprises a second periphery portion opposite to the first periphery portion, adjacent to a third portion of the circuit structure, and configured to dissipate stress between the package structure and the circuit structure, wherein the second periphery portion is asymmetrical to the first periphery portion with respect to a central line of the package structure, wherein a first length of the first periphery portion projecting on the circuit structure is greater from a second length of the second periphery portion projecting on the circuit structure, such that the first portion is allowed to be twisted in a greater extent than the third portion (Figure 18). Regarding claim 20, Low discloses an array of connection elements disposed between the circuit structure and the package structure, wherein, in a bottom view, the array comprises a plurality of rows and a plurality of columns, each of which is non-parallel to a lateral surface of the circuit structure, wherein the package structure comprises a second periphery portion asymmetrical to the first periphery portion with respect to a central line of the package structure, and wherein when the electronic device is under a twisting test at a twisting angle in a range from 300 to 60°, a first portion of the circuit structure proximate to the firs periphery portion has a first curvature and a second portion of the circuit structure proximate to the second periphery portion has a second curvature smaller than the first curvature (Figure 18). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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Prosecution Timeline

Mar 14, 2024
Application Filed
Jan 14, 2026
Non-Final Rejection mailed — §103
Apr 01, 2026
Interview Requested
Apr 10, 2026
Examiner Interview Summary
Apr 10, 2026
Applicant Interview (Telephonic)
Apr 14, 2026
Response Filed
Jul 07, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.3%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 890 resolved cases by this examiner. Grant probability derived from career allowance rate.

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