DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of invention II (claims 8-16) in the reply filed on 06/04/2026 is acknowledged. The traversal is on the ground(s) that “different search-and-examination strategy” that might be required for the Inventions do not appear to be seriously burdensome, especially in view of the fact that the Inventions I and II are deemed closely classified. This is not found persuasive because inventions that are allegedly deemed closely classified do not reduce the burden of examination distinct inventions merely because they may be closely classified (even if they are in the same class/subclass), especially because many class/subclasses have thousands (if not tens of thousands) of references in each subclass.
Furthermore, the processing steps in claims 8-16 would not be necessary to consider with respect to the product claims, e.g., the step of “performing photolithography and development processes” in claim 8 would be need to be considered with respect to the product in claims 1-7, especially because the it is the patentability of the product that must be determined with respect to product claims. There are also specific process sequences (e.g., claim 13) that must be considered in invention II; however, such processing sequences would not be considered with respect to the product claims because it is the patentability of the final product that must be considered. Therefore, the will be a serious burden on the examiner to thoroughly examine product and process claims that are not uniquely related.
The requirement is still deemed proper and is therefore made FINAL.
Claims 1-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 06/04/2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. For example, a more descriptive title could be, “Method of Making Integrated Package Having Second Component Mounted on PID Covering First Component”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0273068 A1; hereinafter, “Chen”) in view of Zwenger et al. (US 2014/0162407 A1; hereinafter, “Zwenger”).
Regarding claim 8:
Chen discloses a method for making an integrated package, comprising:
providing a package (Fig. 3 and [0017]) comprising:
a substrate 30 (Fig. 3 and [0016]); and
a first electronic component 36A (Fig. 3 and [0015]) mounted on the substrate;
forming a first dielectric layer 46 (Fig. 4 and [0019]) on the substrate to cover the first electric component, wherein the first dielectric layer is made of photo imageable dielectric material ([0019] e.g., PBO, BCB);
performing [etching] on the first dielectric layer 46 to form a first through hole 47 in the first dielectric layer (Fig. 5 and [0021]);
forming a first redistribution layer 48A/48B/48B (Fig. 6 and [0022]) in the first dielectric layer, wherein the first redistribution layer comprises a first vertical portion formed in the first through hole and a first lateral portion formed on a top surface of the first dielectric layer; and
mounting a second electronic component 52 (Fig. 7 and [0024]) above the first dielectric layer 46, such that the second electronic component 52 is coupled with the lateral portion of the first redistribution layer 48B/48C; and
forming a second dielectric layer 58 (Fig. 8 and [0026]) above the first dielectric layer 46 to cover the second electric component 52.
Chen does not explicitly disclose what would be included in the etching process for forming the hole 47.
Zwenger shows/teaches it was well known in the art to form an opening in PBO (i.e., a photo imageable dielectric material) by performing photolithography and development processes (e.g., [0052] and Fig. 5L).
It would have been obvious to one of ordinary skill in the art to specifically perform photolithography and development processes to acquire Chen’s opening 47 in PBO material 46 because Zwenger teaches/show it was very well known in the art to form openings in PBO by such processes. In other words, because Chen does not explicitly disclose details of a process for forming the opening 47 in PBO, it would have been obvious to one of ordinary skill in the art to incorporate a well know process as taught/shown by Zwenger.
Regarding claim 9:
Chen discloses the photo imageable dielectric material 46 [0019] comprises one or more of photosensitive polyimide, polybenzoxazole (PBO), phenolic polymers, and benzocyclobutene (BCB) polymers.
Therefore, this claim is rendered obvious by Chen in view of Zwenger.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (in Zwenger) as applied to claim 8 above, and further in view of Bhagavat et al. (US 2019/0326221 A1; hereinafter, “Bhagavat”).
Regarding claim 10:
Chen (in view of Zwenger) does not disclose the second dielectric layer comprises molding compound. However, Bhagavat teaches, in a stacked chip arrangement similar to that of Chen, a molding compound 105 is formed above and covering a first dielectric layer 75 such that a top/last chip 20/25 (Figs. 8-10 and ]0022]) is secured and an upper surface of the top chip is coplanar with the molding compound.
It would have been obvious to one of ordinary skill in the art to specifically incorporate a molding compound for the second dielectric layer of Chen (in view of Zwenger) because Bhagavat teaches such an incorporation would secured the second electric component while allowing its upper surface to be coplanar with the molding compound, wherein such an arrangement could facilitate a heat sink to be placed directly on the top chip.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (in view of Zwenger) as applied to claim 8 above, and further in view of Hu et al. (US 2020/0126923 A1; hereinafter, “Hu”).
Regarding claim 11:
Chen (in view of Zwenger) does not specify how the lateral portion of the first redistribution layer (RDL) is formed.
Hu teaches lateral portions of a RDL are formed by attaching a dry film PR2 (Figs. 7-8 and [0024]) on a first dielectric layer 130a [0022];
performing photolithography and development processes on the dry film to form openings 134a (Fig. 8 and [0024]) at locations where a first through hole 132 (Fig. 6 and [0024]) is exposed and where a lateral portion of a first redistribution layer to be formed; and
filling (NOTE: “filing” should read “filling”) the first through hole in the first dielectric layer and the openings in the dry film with conductive material 138a (Fig. 9 and [0020]) to form a first redistribution layer.
It would have been obvious to one of ordinary skill in the art to specifically incorporate a process as taught by Hu because Chen (in view o Zwenger) does not specify exactly how the lateral portion is made; accordingly, one of ordinary skill in the art would have incorporated any well known process in the art, wherein Hu discloses a well-known process that is well suited for forming lateral portions of an RDL.
Regarding claim 12:
Hu discloses wherein filling (NOTE: “filing” should read “filling”) the openings in the dry film with conductive material comprises:
electroless-plating the conductive material 138a (Fig. 9 and [0025]) on the first dielectric layer and the dry film, such that the conductive material fills the first through hole in the first dielectric layer and the openings in the dry film (Figs. 6-9), and covers a top surface of the dry film [0026]; and
stripping the dry film and the conductive material formed thereon from the first dielectric
layer, such that the conductive material left on the first dielectric layer forms the first
redistribution layer (Fig. 9 and [0025]).
Therefore, claim 12 is rendered obvious by Chen (in view of Zwenger and Hu).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (in view of Zwenger) as applied to claim 8 above, and further in view of Tsai et al. (US 2020/0051949 A1; hereinafter, “Tsai”).
Regarding claim 13:
Chen (in view of Zwenger) does not disclose forming a third dielectric before mounting the second electronic component as currently claimed. However, it is noted the current claim essentially requires forming another dielectric layer in between the first dielectric layer and the second electronic component.
Tsai teaches a plurality of dielectric layers 148/92 (Fig. 35, [0040] and [0053]) incorporated, thereby increasing the number of electronic components (e.g., 36/108) in a stack.
It would have been obvious to one of ordinary skill in the art to modify Chen (in view of Zwenger) by incorporating a third dielectric layer between the first dielectric layer and the second electronic component because Tais teaches multiple dielectric layers could be incorporated such that a number of electronic components in the stack could be increased.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (in view of Zwenger and Tsai) as applied to claim 13 above, and further in view of Hu.
Regarding claim 14:
Chen (in view of Zwenger and Tsai) does not specify electroless-plating conductive material. However, Hu teaches electroless-plating the conductive material 138a (Fig. 9 and [0025]) in a dielectric layer.
It would have been obvious to one of ordinary skill in the art to specifically incorporate an electroless-plating process as taught by Hu because Chen (in view of Zwenger and Tsai) does not specify exactly what type of plating is used; accordingly, one of ordinary skill in the art would have incorporated any well-known plating process in the art, wherein Hu discloses electroless-plating is a well-known process that is well suited for forming RDLs.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (in view of Zwenger and Tsai) as applied to claim 13 above, and further in view of Bhagavat.
Regarding claim 15:
Chen (in view of Zwenger and Tsai) does disclose mounting a third electronic component on the lateral portion of the first RDL.
Bhagavat teaches at least two electronic components 20/25 mounted on lateral portions of a RDL (Figs. 8-10).
It would have been obvious to one of ordinary skill in the art to modify Chen (in view of Zwenger and Tsai) by mounting a third electronic component, as taught by Bhagavat, because the modification would provide increased functionality to the stacked IC because the number of electronic components in the stack would be increased.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (in view of Zwenger and Tsai) as applied to claim 13 above, and further in view of Law et al. (US 2015/0303172 A1; hereinafter, “Law”).
Regarding claim 16:
Chen (in view of Zwenger and Tsai) does not disclose forming an EMI shielding layer. However, Law teaches an EMI shielding layer 358 (Fig. 3A and [0055]) can protect stacked dies from external EMI.
It would have been obvious to one of ordinary skill in the art to incorporate an EMI shielding layer into the stacked packaged of Chen (in view of Zwenger and Tsai) because Law teaches such a layer protects stacked dies from external EMI.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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