Prosecution Insights
Last updated: October 04, 2026
Application No. 18/605,842

PARTIALLY SHIELDED SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME

Non-Final OA §102§103
Filed
Mar 15, 2024
Priority
Apr 04, 2023 — CN 202310351921.1
Examiner
MALSAWMA, LALRINFAMKIM HMAR
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Stats Chippac Pte. Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
1007 granted / 1113 resolved
+22.5% vs TC avg
Moderate +9% lift
Without
With
+8.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
30 currently pending
Career history
1141
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
43.3%
+3.3% vs TC avg
§102
35.6%
-4.4% vs TC avg
§112
10.2%
-29.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1113 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Invention I (claims 1-10) in the reply filed on 06/04/2026 is acknowledged. The traversal is on the ground(s) that “different search-and-examination strategy” that might be required for the Inventions do not appear to be seriously burdensome, especially in view of the fact that the Inventions I and II are deemed closely classified. This is not found persuasive because inventions that are allegedly deemed closely classified do not reduce the burden of examining distinct inventions merely because they may be closely classified (or even if they are in the same class/subclass), especially because many class/subclasses have thousands (if not tens of thousands) of references in each subclass. Furthermore, it would not be necessary to consider the processing steps in claims 1-10 with respect to the product claims, e.g., the steps of “performing a laser hatching process” and “electroless-plating” in claim 1 would not be considered with respect to the product in claims 11-15, especially because it is the patentability of the product that must be determined with respect to product claims and not the patentability of the process for making the product. Therefore, there will be a serious burden on the examiner to thoroughly examine simultaneously both product and process claims that are not uniquely related. The requirement is still deemed proper and is therefore made FINAL. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3, 5, 7, 9 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dang et al. (US 2016/0351509 A1; hereinafter, “Dang”). Regarding claims 1, 3, 5, 7, 9 and 10: re claim 1, Dang discloses a method for making a partially shielded semiconductor device, comprising: providing a package (Fig. 3G) comprising: a substrate 38/46/50 [0023, 0024, 0025]; an electronic component 16/18 [0020] mounted on the substrate; an encapsulant 20 [0020] formed on the substrate and encapsulating the electronic component; and a coating layer 30 [0022] formed on the substrate and adjacent to the encapsulant; performing a laser hatching process (Fig. 3H and [0027], wherein laser drilling is considered to be a “laser hatching process”) on the encapsulant 20 and a portion of the coating layer 30 adjacent to the encapsulant to remove the portion of the coating layer 30 to form a trench 54 (Fig. 3H and [0027]) between the encapsulant and the coating layer; and electroless-plating a conductive material 66 (Fig. 3J and [0029]) to cover the encapsulant 20 and fill the trench 54 between the encapsulant and the coating layer; re claim 3, the method of claim 1, wherein providing the package comprises: providing the substrate 38/46/50 (Figs. 3B-3F); forming the coating layer 30 on the substrate (i.e., when the substrate is provided in Figs. 3B-3F, the coating layer 30 is formed on the substrate); mounting (Note: “mounted” should read “mounting”) the electronic component 16/18 on the substrate (Figs. 3B-3F, i.e., when the substrate is provided in Figs. 3B-3F, the electronic component 16/18 is mounted on the substrate); and forming the encapsulant 20 on the coating layer 30 (Fig. 3A-3B) to encapsulate the electronic component 16/18; re claim 5, the method of claim 1, wherein providing the package comprises: providing the substrate 38/46/50 (Figs. 3B-3F); mounting (Note: “mounted” should read “mounting”) the electronic component on the substrate (Figs. 3B-3F, i.e., when the substrate is provided in Figs. 3B-3F, the electronic component 16/18 is mounted on the substrate); forming the encapsulant 20 on the coating layer 30 (Fig. 3A-3B) to encapsulate the electronic component 16/18; and forming the coating layer 30 to cover [a bottom side of] the encapsulant 20 and [a top side of] the substrate 38/46/50 (Figs. 3B-3F); re claim 7, Dang discloses each of the dies 16/18 is connected to ground, i.e., each die has an I/O port at a bottom surface connected to ground [0020]; accordingly, the I/O port is considered to be a ground pad, and the substrate comprises a connection pad 48 (Fig. 3E) that is farther away from the electronic component 16/18 than the ground pad (which is on a surface of the electronic component [0020]). re claim 9, the method of claim 7, wherein the coating layer 30 (Fig. 3E) covers [an upper side of] the connection pad 48; and re claim 10, the method of claim 1, further comprising removing the coating layer 30 from the substrate (Figs. 3G-3H, wherein at least a portion of the coating layer 30 is removed when forming trench 54). Therefore, Dang anticipates claims 1, 3, 5, 7 ,9 and 10. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 2 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dang. PNG media_image1.png 902 1572 media_image1.png Greyscale Regarding claim 2: Dang anticipates claim 1 and discloses the coating layer 30 may be BCB, polyimide or other dielectric materials [0022]. It is noted BCB and polyimide comprise a surfactant, and although they are typically free of a thiol functional organic compound, Dang specifies other dielectrics can be used. Therefore, it would have been obvious to one of ordinary skill in the art to modify Dang by incorporating any well-known, commercially available dielectric material such as Selectcoat 100 FL, which is a coating layer comprising a thiol functional organic compound and a surfactant, especially because Selectcoat 100 FL captures debris during laser structuring (e.g., see above, disclosure by MacDermid Alpha regarding Selectcoat 100 FL). Regarding claim 8: Dang does not disclose the trench exposes the ground pad; however, Dang discloses the trench 54 (Fig. 3I) exposes copper structure 38 [0023]; and because the copper structure 38 is directly connected to a surface of the electronic component, it would have been obvious to one of ordinary skill in the art to connect copper structure 38 (exposed by the trench) to ground such that the shielding structure 62 (Fig. 3J and [0029]) is grounded to protect the component from EMI or crosstalk (e.g., [0004]). Claim(s) 4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dang in view of Cho (US 2014/0008772 A1, which is a prior art of record listed on the IDS, filed 03/15/2024). Regarding claims 4 and 6: Dang anticipates claims 3 and 5but does not disclose the encapsulant has a plurality of light-sensitive particles dispersed therein. Cho teaches an encapsulant 250 (Fig. 1) having a plurality of light-sensitive particles 255 (Fig. 8A) dispersed therein. Cho discloses the light-sensitive particles are transformed to conductive particles the are used as a seed layer [0013]. It would have been obvious to one of ordinary skill in the art to modify Dang by incorporating light-sensitive particles into the encapsulant, as taught by Cho, because the modification would provide a seed layer for the conductive material covering the encapsulant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LEX H MALSAWMA/Primary Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Mar 15, 2024
Application Filed
Aug 24, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+8.8%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1113 resolved cases by this examiner. Grant probability derived from career allowance rate.

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