Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/15/24, 06/04/25, 10/15/25 were filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims #1, 2 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims #16 of Hsiung et al., (U.S. Patent No. 11,967,526), hereinafter referred to as "Hsiung". Although the claims at issue are not identical, they are not patentably distinct from each other because;
Claim #1 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #16 of Hsiung, U.S. Patent No. 11,967,526, which discloses, a device comprising: a gate structure; a dielectric cap over the gate structure, a top portion of the dielectric cap being an oxidized region, a bottom portion of the dielectric cap being an un-oxidized region between the gate structure and the oxidized region; a source/drain contact adjacent to the gate structure; an interlayer dielectric (ILD) layer over the dielectric cap and the source/drain contact; and a source/drain via in the ILD layer and electrically connected to the source/drain contact. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #16, of U.S. Patent No. 11,967,526, produces the same semiconductor structure as that in claim #1 of the instant application, which states, semiconductor structure, comprising: a semiconductive fin; a gate structure extending across the semiconductive fin; a plurality of source/drain regions over the semiconductive fin and at opposite sides of the gate structure; an un-oxidized dielectric cap atop the gate structure; and an oxidized dielectric cap atop the oxidized dielectric cap.
Claim #2 is rejected on the grounds of nonstatutory obviousness-type double patenting as being unpatentable over claim #16 of Hsiung, U.S. Patent No. 11,967,526, which discloses, a device comprising: a gate structure; a dielectric cap over the gate structure, a top portion of the dielectric cap being an oxidized region, a bottom portion of the dielectric cap being an un-oxidized region between the gate structure and the oxidized region; a source/drain contact adjacent to the gate structure; an interlayer dielectric (ILD) layer over the dielectric cap and the source/drain contact; and a source/drain via in the ILD layer and electrically connected to the source/drain contact. Although the conflicting claims are not identical, they are not patentably distinct from each other because it would have been obvious to one ordinarily skilled in the art to understand that the claimed structure of claim #16, of U.S. Patent No. 11,967,526, produces the same semiconductor structure as that in claim #2 of the instant application, which states, semiconductor structure, comprising: a semiconductive fin; a gate structure extending across the wherein the oxidized dielectric cap forms an interface with the un-oxidized dielectric cap.
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Claim #3, 4, 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims #16 of Hsiung et al., (U.S. Patent No. 11,967,526), hereinafter referred to as "Hsiung" as shown in the rejection of claim #1 above and in view of Wang et al., (U.S. Pub. No. 2018/0166576), hereinafter referred to as “Wang”.
Hsiung substantially shows the claimed invention as shown in the rejection claim #1 above.
Hsiung, with respect to claim #3, fails to show wherein the un-oxidized dielectric cap and the oxidized dielectric cap comprise a same chemical element.
Wang teaches, with respect to claim #3, wherein the un-oxidized dielectric cap (fig. #16, item 250) and the oxidized dielectric cap (fig. #16, item 230) comprise a same chemical element (paragraph 0037).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #3, to modified the invention of Hsiung, with the modifications taught by Wang invention, which teaches, wherein the un-oxidized dielectric cap and the oxidized dielectric cap comprise a same chemical element, to incorporate a structural condition that would provide etching conditions favorable structural dynamics and control capacitance of the device area, as taught by Wang.
Hsiung, with respect to claim #4, fails to show wherein the un-oxidized dielectric cap is made of silicon nitride.
Wang teaches, with respect to claim #4, wherein the un-oxidized dielectric cap is made of silicon nitride (paragraph 0037).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #4, to modified the invention of Hsiung, with the modifications taught by Wang invention, which teaches, wherein the un-oxidized dielectric cap is made of silicon nitride, to incorporate a structural condition that would provide etching conditions favorable structural dynamics and control capacitance of the device area, as taught by Wang.
Hsiung, with respect to claim #10, fails to show an etch stop layer over the oxidized dielectric cap.
Wang teaches, with respect to claim #10, further comprising: an etch stop layer (fig. #3&5, item 144) over the oxidized dielectric cap (paragraph 0008, 0012-0013).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #10, to modified the invention of Hsiung, with the modifications taught by Wang invention, which teaches further comprising: an etch stop layer over the oxidized dielectric cap, to incorporate a structural condition that would provide etching conditions favorable structural dynamics and control capacitance of the device area, as taught by Wang.
Allowable Subject Matter
Claims #5-9, 21-30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: While the prior art teaches a semiconductor structure, comprising: a semiconductive fin; a gate structure extending across the semiconductive fin; a plurality of source/drain regions over the semiconductive fin and at opposite sides of the gate structure; an un-oxidized dielectric cap atop the gate structure; and an oxidized dielectric cap atop the oxidized dielectric cap, (Hsiung et al., 11,967,526; Wang et al., 2018/0166576), it fails to teach either collectively or alone, with respect to claim #5, wherein the oxidized dielectric cap has an oxygen atomic percentage decreasing as a distance from a top surface of the oxidized dielectric cap increases. Also, the prior art fails to teach either collectively or alone, with respect to claim #6, a semiconductor structure, further comprising: a metal contact over one of the source/drain regions; and a metal via over the metal contact and in contact with a top surface of the un-oxidized dielectric cap exposed from the oxidized dielectric cap. Furthermore, with respect to claim #7, the prior art fails to teach either collectively or alone, a semiconductor structure, a metal contact over one of the source/drain regions; and a metal oxide layer over the metal contact. Also, with respect to claim #9, the prior art fails to teach either collectively or alone, a semiconductor structure further comprising: a butted contact downwardly extending through the oxidized dielectric cap and the un- oxidized dielectric cap. Furthermore, the prior art fails to teach either collectively or alone, with respect to claim #21, a semiconductor structure comprising a source/drain via extending through the dielectric layer to the source/drain contact, wherein a bottom surface of the source/drain via comprises a first portion in contact with the source/drain contact and a second portion laterally offset from the source/drain contact and in contact with the oxidized dielectric region of the dielectric cap. Also, the prior art fails to teach either collectively or alone, with respect to claim #26, a semiconductor structure comprising a butted contact extending through the dielectric layer, the oxidized dielectric region, and the un-oxidized dielectric region to the metal cap, wherein the butted contact is further in contact with the source/drain contact.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683. The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2816
07/02/2026
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights