Prosecution Insights
Last updated: July 17, 2026
Application No. 18/606,384

SEMICONDUCTOR DEVICE WITH NECK LAYER AND METHOD FOR FABRICATING THE SAME

Non-Final OA §102
Filed
Mar 15, 2024
Examiner
WARREN, MATTHEW E
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NANYA TECHNOLOGY Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
879 granted / 1003 resolved
+19.6% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
17 currently pending
Career history
1024
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
69.9%
+29.9% vs TC avg
§102
25.8%
-14.2% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1003 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US Pub. 2015/0214291 A1). In re claim 1, Park et al. shows (fig. 2) a semiconductor device, comprising: a substrate (110); at least two bit line structures (central BLS-not labeled and BLS-140) positioned on the substrate; a contact layer (170A) positioned on the substrate and between the at least two bit line structures; and a conductive neck layer (170B) positioned on the contact layer and between the at least two bit line structures; wherein a width of a top surface of the conductive neck layer is greater than a width of a bottom surface of the conductive neck layer (since the conductive neck layer 170B has a wider width W3 than at the bottommost surface). In re claims 2-13, Park et al. shows (fig. 2) the remaining elements of the claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee (US Pub. 2022/0115382 A1), Kim (US Pub. 2021/0134808 A1), Kim (US Pub. 2015/0214146 A1), Lu (WO-2024065989-A1) and Park (KR-20210032595-A) also disclose various elements of the claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW E WARREN/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Mar 15, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12684882
IMAGE SENSOR PACKAGE AND METHOD OF FABRICATING THE SAME
3y 2m to grant Granted Jul 14, 2026
Patent 12677490
PHOTOELECTRIC CONVERSION DEVICE
3y 0m to grant Granted Jul 07, 2026
Patent 12677424
THREE-DIMENSIONAL FERROELECTRIC MEMORY DEVICE
3y 0m to grant Granted Jul 07, 2026
Patent 12666605
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
3y 7m to grant Granted Jun 23, 2026
Patent 12666622
NON-VOLATILE MEMORY DEVICE AND SYSTEM INCLUDING THE SAME
2y 11m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+5.6%)
2y 7m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1003 resolved cases by this examiner. Grant probability derived from career allowance rate.

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