DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention Group II, Embodiment 2 of Figure 14B, Claims 1-12 and 21-28, in the reply filed on 06/15/2026 is acknowledged. The traversal is on the ground(s) that Figures 16A/16B illustrate the details of the dies 10’ in Figures 14A-14C and hence cannot possibly be mutually exclusive. This is found persuasive. Accordingly, the restriction of Figures 16A/16B from Figures 14A-14C is withdrawn.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 9-12, 21 and 24 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tseng et al. (US 2024/0339370).
Regarding claim 1, Tseng et al. discloses, as shown in Figures 1-12, a method comprising:
forming a first die (10’) comprising:
forming a first metal pillar (30, [0017]) on a first side of a first semiconductor substrate (12) of the first die;
polishing the first semiconductor substrate of the first die to reveal a first through-via (16) in the first semiconductor substrate (Figure 2, [0020]); and
forming a second metal pillar (40, [0026]-[0029], damascene process with straight sidewalls forming the post or pillar) on a second side of the first die, wherein the first side and the second side are on opposite sides of the first semiconductor substrate; encapsulating the first die in an encapsulant (66);
forming a first conductive feature (60) on the first side of the first semiconductor substrate and electrically connecting to the first metal pillar; and
forming a second conductive feature (72) on the second side of the first semiconductor substrate and electrically connecting to the second metal pillar (Figure 12).
Regarding claim 4, Tseng et al. discloses the method further comprising bonding a first package component (74) and a second package component (74) over the first die, wherein the first die electrically connects the first package component to the second package component (Figure 13).
Regarding claim 5, Tseng et al. discloses the forming the second metal pillar comprises a plating process ([0026]-[0029]).
Regarding claim 9, Tseng et al. discloses the encapsulant is filled into spaces between the first metal pillar and an additional first metal pillar of the first die.
Regarding claim 10, Tseng et al. discloses the method further comprising, before the first die is encapsulated in the encapsulant, attaching a supporting substrate (46) to the first die (Figure 6).
Regarding claim 11, Tseng et al. discloses the method further comprising, before the first die is encapsulated in the encapsulant, thinning the supporting substrate ([0031]-[0032]).
Regarding claim 12, Tseng et al. discloses the method further comprising, after the first die is encapsulated in the encapsulant, performing a planarization process to remove the supporting substrate ([0031]-[0032]).
Regarding claim 21, Tseng et al. discloses, as shown in Figures 1-13, a method comprising:
forming a first interconnect die (10’) comprising:
forming a first through-via (16) in a first semiconductor substrate (12); and
forming a first metal pillar (30, [0017]) and a second metal pillar (40, [0026]-[0029], damascene process with straight sidewalls forming the post or pillar) at opposite surfaces of the first interconnect die, wherein at least one of the first metal pillar and the second metal pillar is electrically connected to the first through-via; and
applying an encapsulant (66) to encapsulate the first interconnect die in the encapsulant.
Regarding claim 24, Tseng et al. discloses the method further comprising:
forming a first dielectric layer (58) contacting a first surface of the first interconnect die;
forming a first conductive feature (60) in the first dielectric layer and contacting the first metal pillar;
forming a second dielectric layer (70) contacting a second surface of the first interconnect die, wherein the second surface is opposite to the first surface; and
forming a second conductive feature (72) in the second dielectric layer and contacting the second metal pillar (Figures 12).
Claim(s) 21 and 24 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Karhade et al. (US 2023/0092821).
Regarding claim 21, Karhade et al. discloses, as shown in Figures 1-5C, a method comprising:
forming a first interconnect die (102,202) comprising:
forming a first through-via (not shown, [0070]) in a first semiconductor substrate (portion of 102,202); and
forming a first metal pillar (151, [0090]) and a second metal pillar (153, [0090]) at opposite surfaces of the first interconnect die, wherein at least one of the first metal pillar and the second metal pillar is electrically connected to the first through-via ([0070]); and
applying an encapsulant (133) to encapsulate the first interconnect die in the encapsulant (Figure 5C).
Regarding claim 24, Karhade et al. discloses the method further comprising:
forming a first dielectric layer (127) contacting a first surface of the first interconnect die;
forming a first conductive feature (130) in the first dielectric layer and contacting the first metal pillar;
forming a second dielectric layer (127) contacting a second surface of the first interconnect die, wherein the second surface is opposite to the first surface; and
forming a second conductive feature (150) in the second dielectric layer and contacting the second metal pillar (Figures 1-5C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al. (US 2024/0339370).
Regarding claims 7-8, Tseng et al. discloses all of the claimed limitations except material of the insulating layers. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the insulating layers of Tseng et al. having the materials as that claimed by Applicant, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Allowable Subject Matter
Claims 2-3, 6, 22-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 25-28 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The second die comprising forming a third metal pillar on a firs side of a second semiconductor substrate of the second die, wherein the third metal pillar and the firs metal pillar have different heights, in combination with the remaining claimed limitations of claim 2; the first metal pillar and the second metal pillar have a same aspect ratio, as recited in claim 6; the second interconnect die comprises a third metal pillar and a fourth metal pillar at opposite surfaces of the second interconnect die, wherein the firs metal pillar and the second metal pillar have a first total thickness, and the third metal pillar and the fourth metal pillar have a second total thickness different from the first total thickness, in combination with the remaining claimed limitations of claim 22; the first metal pillar and the second metal pillar have a same aspect ratio, as recited in claim 23.
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897 /HUNG K VU/Primary Examiner, Art Unit 2897
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