DETAILED ACTION
This Office action responds to the application filed on 03/18/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation "the gate contact regions" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102 & 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, & 3 are rejected under 35 U.S.C. 103 as being unpatentable over Mori (US 20260032990) in view of Potera (US 20230420451).
Regarding Claim 1, Mori (see, e.g., fig. 1) shows a semiconductor device, comprising:
a semiconductor layer structure 6 & 7 (see, e.g., para.0043-0044) that comprises
a termination region 9 (see, e.g., para.0050)
and an active region 8 (portion of 8 surrounding gate pad 80, see, e.g., para.0048) that comprises a plurality of gate regions 30 (see, e.g., fig. 7, para.0113);
a gate pad 80 (see, e.g., fig. 1, para.0289) on the semiconductor layer structure;
a gate bus 44 & 70 (see, e.g., para.0161, para.0266) that is electrically connected to the gate pad 80 (connected to 44 via second embedded electrodes 72, see, e.g., para.0294);
Mori, however, fails to show
and a gate resistor
and the gate resistor that is interposed between the gate bus and at least some of the gate regions when the semiconductor device is viewed in plan view.
Potera (see, e.g., fig. 1, fig. 2a, fig. 14, para.0113), in a similar device to Mori, teaches
and a gate resistor 32r
and the gate resistor 32r that is interposed between the gate bus 38b and at least some of the gate regions 38c (active area comprising 38c & 32c)
Potera states including the gate resistor 32r in this configuration of a JFET can increase the gate resistance.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of the gate resistor of Potera in the device of Mori to increase the gate resistance.
The gate resistor of Potera 32r is incorporated in the device of Mori (portion of concentration region 10, hereinafter referred to as “10R”) as shown in the following figure.
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Regarding Claim 2, Mori, in view of Potera, shows the semiconductor device of 3 Claim 1,
wherein the gate resistor 10R extends fully along at least two sides of the active region when the semiconductor device is viewed in plan view (see, e.g., following annotated figure).
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Regarding Claim 3, Mori, in view of Potera, shows the semiconductor device of Claim 2, further comprising
a termination resistor (12 portion of concentration region 10, hereinafter referred to as “10T”, see, e.g., following annotated figure) that extends around a periphery of the gate bus 44 & 70 when the semiconductor device is viewed in plan view (see, e.g., following annotated figure).
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Claims 5, 6, 9, & 11 are rejected under 35 U.S.C. 103 as being unpatentable over Mori (US 20260032990) in view of Potera (US 20230420451) and further in view of Kouno (US 20230042174).
Regarding Claim 5, Mori, in view of Potera, shows the semiconductor device of Claim 1,
wherein the semiconductor device comprises
a junction field effect transistor (“JFET”) (see, e.g., fig. 2, para.0100)
Mori, in view of Potera, however, fails to show
wherein the semiconductor device comprises
the junction field effect transistor ("JFET") having
a JFET gate terminal,
a JFET source terminal
and a JFET drain terminal
Kouno (see, e.g., fig. 1, fig. 2, fig. 7, para.0063), in a similar device to Mori, in view of Potera, teaches a configuration
wherein the semiconductor device comprises
a junction field effect transistor ("JFET") 10 (see, e.g., para.0031, para.0039) having
a JFET gate terminal 13,
a JFET source terminal 11
and a JFET drain terminal 12,
Kouno (see, e.g., para.0107-0108) states the configuration of including a JFET along with a MOSFET would reduce a switching loss of the semiconductor device.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Kouno in the device of Mori, in view of Potera, to reduce a switching loss of the semiconductor device.
Regarding Claim 6, Mori, in view of Potera and further in view of Kouno (see, e.g., fig. 1, para.0027, para.0031, para.0029, para.0053), shows the semiconductor device of Claim 5,
wherein the JFET comprises
a silicon carbide-based JFET (see, e.g., para.0031, para.0039)
and the semiconductor device is provided in combination with a silicon-based metal-oxide-semiconductor field-effect transistor ("MOSFET") 20 (see, e.g., para.0031, para.0053)
and the silicon carbide-based JFET is cascoded with the silicon-based MOSFET (see, e.g., para.0027).
Regarding Claim 9, Mori, in view of Potera and further in view of Kouno, shows the semiconductor device of Claim 5,
wherein an intrinsic gate-to-drain capacitance of the JFET comprises
an active region 8 gate-to-drain capacitance (formed from gate electrode 32 to drain pad electrode 85, see, e.g., following annotated figure)
and a termination region 9 gate-to-drain capacitance (formed from gate electrode 32 to drain pad electrode 85, see, e.g., following annotated figure),
and wherein the active region gate-to-drain capacitance is electrically in series with the gate resistor 10R (see, e.g., following annotated figure)
and the termination region gate-to-drain capacitance is not electrically in series with the gate resistor 10R (see, e.g., following annotated figure).
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Regarding Claim 11, Mori, in view of Potera and further in view of Kouno, shows the semiconductor device of Claim 9,
wherein the intrinsic gate-to-drain capacitance of the JFET further comprises
a gate pad/bus region (regions of 44, 70, & 80) gate-to-drain capacitance that is electrically in parallel with the gate resistor (under gate pad 80, formed from gate electrode 32 to drain pad electrode 85, see previous annotated figure).
Claims 1, 12, 13, 15, 16, & 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Potera (US 20230420451).
Regarding Claim 1, Potera shows a semiconductor device, comprising:
a semiconductor layer structure 5 (see, e.g., para.0076) that comprises
a termination region (see, e.g., following annotated figure) and an active region that comprises a plurality of gate regions 38c (portion of active area surrounding 32r & 38b, see, e.g., fig. 2b, following annotated figure);
a gate pad 38p (see, e.g., para.0076) on the semiconductor layer structure;
a gate bus 38b (see, e.g., para.0076) that is electrically connected to the gate pad;
and a gate resistor 32r (see, e.g., para.0076) that is interposed between the gate bus and at least some of the gate regions when the semiconductor device is viewed in plan view (see, e.g., para.0076, fig. 1).
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Regarding Claim 12, Potera shows the semiconductor device of Claim 1,
wherein the semiconductor layer structure includes
a drift region 20 (see, e.g., para.0070) having a first conductivity type (n-type)
and a patterned region 32 (see, e.g., para.0080) that has a second conductivity type (p-type) on the drift region,
where the gate resistor 32r is formed in a portion of the patterned region (see, e.g., para.0083).
Regarding Claim 13, Potera shows the semiconductor device of Claim 12,
wherein the semiconductor layer structure further comprises a channel region 30 (see, e.g., para.0078) having the first conductivity type (n-type) on the drift region,
where a first conductivity type dopant concentration of the channel region exceeds a first conductivity type dopant concentration of the drift region (see, e.g., para.0078x`),
and wherein the patterned region 32 is at least partially formed within the channel region 30 (see, e.g., para.0080).
Regarding Claim 15, Potera shows the semiconductor device of Claim 12,
wherein the gate pad 32p and the gate bus 38b are each formed directly on the patterned region 32 (see, e.g., fig. 2b).
Regarding Claim 16, Potera shows the semiconductor device of Claim 15,
wherein the gate pad 38p comprises a metal gate pad region 37p (see, e.g., para.0089) and a metal silicide gate pad region 35p (see, e.g., para.0097),
the gate bus 38b comprises a metal gate bus region 37b (see, e.g., para.0089) and a metal silicide gate bus region 35b (see, e.g., para.0089),
and the gate resistor comprises a portion of the patterned region that has an upper surface that is devoid of any metal silicide (see, e.g., para.0090).
Regarding Claim 19, Potera shows the semiconductor device of Claim 12,
wherein the gate contact regions 32c (see, e.g., para.00083) are part of the patterned region 32.
Claim 22, 24, 25, & 26 are rejected under 35 U.S.C. 103 as being unpatentable over Mori (US 20260032990) in view of Potera (US 20230420451).
Regarding Claim 22, Mori (see, e.g., fig. 1) shows a semiconductor device, comprising:
a semiconductor layer structure 6 & 7 (see, e.g., para.0043-0044) that comprises
an active region 8 (see, e.g., para.0048),
a gate pad/bus region (region of 44, 70, & 80, see, e.g., fig. 1, fig. 8)
and a termination region 9 (see, e.g., para.0050);
a plurality of gate regions 30 (see, e.g., fig. 7, para.0113);
a gate pad 80 (see, e.g., fig. 1, para.0289) on the gate pad/bus region of the semiconductor layer structure;
wherein an intrinsic gate-to-drain capacitance of the semiconductor device comprises
an active region 8 gate-to-drain capacitance (formed from gate electrode 32 to drain pad electrode 85, see, e.g., following annotated figure),
a gate pad/bus region gate-to-drain capacitance (under gate pad 80, formed from gate electrode 32 to drain pad electrode 85, see, e.g., following annotated figure)
and a termination region gate-to-drain capacitance (formed from gate electrode 32 to drain pad electrode 85, see, e.g., following annotated figure),
Mori, however, fails to show
and a gate resistor that is electrically connected between the gate pad and the gate regions,
and wherein the active region gate-to-drain capacitance is electrically coupled in series with the gate resistor
and the termination region gate-to-drain capacitance is not electrically coupled in series with the gate resistor
Potera (see, e.g., fig. 1, fig. 2a, fig. 14, para.0113), in a similar device to Mori, teaches
and a gate resistor 32r
Potera states including the gate resistor 32r in the configuration of a JFET can increase the gate resistance.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of the gate resistor of Potera in the device of Mori to increase the gate resistance.
The gate resistor of Potera 32r is incorporated in the device of Mori (portion of concentration region 10, hereinafter referred to as “10R”) as shown in the following figure.
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The gate resistor of Mori, in view of Potera, would teach the missing limitations
and wherein the active region gate-to-drain capacitance is electrically coupled in series with the gate resistor (see, e.g., following annotated figure)
and the termination region gate-to-drain capacitance is not electrically coupled in series with the gate resistor (see, e.g., following annotated figure)
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Regarding Claim 24, Mori, in view of Potera, shows the semiconductor device of Claim 22, further comprising
a gate bus 44 & 70 (see, e.g., para.0161, para.0266) that is electrically connected to the gate pad 80 (connected to 44 via second embedded electrodes 72, see, e.g., para.0294),
the gate resistor 10R is electrically interposed between the gate bus 44 & 70 and at least some of the gate regions 30 (see, e.g., following annotated figure).
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Regarding Claim 25, Mori, in view of Potera, shows the semiconductor device of Claim 24, further comprising
a termination resistor (12 portion of concentration region 10, hereinafter referred to as “10T”, see, e.g., following annotated figure) that extends around a periphery of the gate bus 44 & 70 when the semiconductor device is viewed in plan view.
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Regarding Claim 26, Mori, in view of Potera, shows the semiconductor device of Claim 25,
wherein the gate bus 44 & 70 and the gate pad 80 are both interposed between the gate resistor 10R and the termination resistor 10T when the semiconductor device is viewed in plan view (see, e.g., following annotated figure).
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Claims 32, 33, & 34 are rejected under 35 U.S.C. 103 as being unpatentable over Mori (US 20260032990) in view of Potera (US 20230420451).
Regarding Claim 32, Mori (see, e.g., fig. 1) shows a semiconductor device, comprising:
a semiconductor layer structure 6 & 7 (see, e.g., para.0043-0044);
a plurality of gate regions 30 (see, e.g., fig. 7, para.0113) in the semiconductor layer structure;
a gate pad 80 (see, e.g., fig. 1, para.0289) on the semiconductor layer structure;
a gate bus 44 & 70 (see, e.g., para.0161, para.0266) on the semiconductor layer structure;
where the gate pad is directly electrically connected to the gate bus (80 connected to 44 via second embedded electrodes 72, see, e.g., para.0294),
Mori, however, fails to show,
and a gate resistor in the semiconductor layer structure,
the gate resistor is electrically interposed between the gate bus and at least some of the gate regions.
Potera (see, e.g., fig. 1, fig. 2a, fig. 14, para.0113), in a similar device to Mori, teaches
and a gate resistor 32r in the semiconductor layer structure 5
the gate resistor 32r is electrically interposed between the gate bus 38b and at least some of the gate regions 38c (active area comprising 38c & 32c)
Potera states including the gate resistor 32r in this configuration of a JFET can increase the gate resistance.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of the gate resistor of Potera in the device of Mori to increase the gate resistance.
The gate resistor of Potera 32r is incorporated in the device of Mori (portion of concentration region 10, hereinafter referred to as “10R”) as shown in the following figure.
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Regarding Claim 33, Mori, in view of Potera, shows the semiconductor device of Claim 32, further comprising
a termination resistor (12 portion of concentration region 10, hereinafter referred to as “10T”, see, e.g., following annotated figure) that extends around a periphery of the gate bus 44 & 70 when the semiconductor device is viewed in plan view (see, e.g., following annotated figure).
Regarding Claim 34, Mori, in view of Potera, shows the semiconductor device of Claim 33,
wherein both the gate pad 80 and the gate bus 44 & 70 are interposed between the gate resistor 10R and the termination resistor 10T when the semiconductor device is viewed in plan view.
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Claims 35, 36, 37, & 38 are rejected under 35 U.S.C. 103 as being unpatentable over Mori (US 20260032990) in view of Potera (US 20230420451) and further in view of Kouno (US 20230042174).
Regarding Claim 35, Mori, in view of Potera, shows the semiconductor device of Claim 32,
wherein the semiconductor device comprises
a silicon carbide-based junction field effect transistor ("JFET") (see, e.g., fig. 2, para.0100)
Mori, in view of Potera, however, fails to show
wherein the semiconductor device comprises
the silicon carbide-based junction field effect transistor ("JFET") having
a JFET gate terminal,
a JFET source terminal
and a JFET drain terminal,
and the semiconductor device is provided in combination with a silicon-based metal-oxide-semiconductor field-effect transistor ("MOSFET") that comprises
a MOSFET gate terminal,
a MOSFET source terminal
and a MOSFET drain terminal,
and wherein the MOSFET source terminal is coupled to the JFET gate terminal and the MOSFET drain terminal is coupled to the JFET source terminal.
Kouno (see, e.g., fig. 1, fig. 2, fig. 7, para.0063), in a similar device to Mori, in view of Potera, teaches a configuration
wherein the semiconductor device comprises
a silicon carbide-based junction field effect transistor ("JFET") 10 (see, e.g., para.0031, para.0039) having
a JFET gate terminal 13,
a JFET source terminal 11
and a JFET drain terminal 12,
and the semiconductor device is provided in combination with a silicon-based metal-oxide-semiconductor field-effect transistor ("MOSFET") 20 (see, e.g., para.0031, para.0053) that comprises
a MOSFET gate terminal 23,
a MOSFET source terminal 21
and a MOSFET drain terminal 22,
and wherein the MOSFET source terminal is coupled to the JFET gate terminal and the MOSFET drain terminal is coupled to the JFET source terminal (see, e.g., para.0032-0033).
Kouno (see, e.g., para.0107-0108) states the configuration of including a JFET along with a MOSFET would reduce a switching loss of the semiconductor device.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Kouno in the device of Mori, in view of Potera, to reduce a switching loss of the semiconductor device.
Regarding Claim 36, Mori, in view of Potera and further in view of Kouno, shows the semiconductor device of Claim 35,
wherein the semiconductor layer structure includes
an active region 8 (portion of 8 surrounding gate pad 80, see, e.g., para.0048),
a gate pad/bus region (regions of 44, 70, & 80)
and a termination region 9 (see, e.g., para.0050),
the termination region at least partially surrounding the active region (see, e.g., fig. 1).
Regarding Claim 37, Mori, in view of Potera and further in view of Kouno, shows the semiconductor device of Claim 36,
wherein an intrinsic gate-to-drain capacitance of the JFET comprises
an active region 8 gate-to-drain capacitance (formed from gate electrode 32 to drain pad electrode 85, see, e.g., following annotated figure)
and a termination region 9 gate-to-drain capacitance (formed from gate electrode 32 to drain pad electrode 85, see, e.g., following annotated figure),
and wherein the active region gate-to-drain capacitance is electrically in series with the gate resistor 10R (see, e.g., following annotated figure)
and the termination region gate-to-drain capacitance is not electrically in series with the gate resistor 10R (see, e.g., following annotated figure).
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Regarding Claim 38, Mori, in view of Potera and further in view of Kouno, shows the semiconductor device of Claim 37,
wherein the termination region gate-to-drain capacitance is electrically in parallel with the gate resistor (see, e.g., previous annotated figure).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2818
Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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