DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 02/03/2026 have been fully considered but they are not persuasive.
First of all, Applicant argued that Narayanan is limited to reset-time initialization and does not disclose the reuse of manufacturing-generated patterns for in-field testing, and that Al-Asaad does not disclose the provenance of the patterns. The Examiner respectfully disagrees because a person of ordinary skill in the art (PHOSITA) reading these references would understand that deterministic test patterns are inherently generated during the design and manufacturing phase. Al-Asaad explicitly teaches the use of “deterministic test sequences” for “on-line testing” to detect operational faults in the field. The paper states that these are “complete test sets” for stuck-at faults, which are the product of ATPG (Automatic Test Pattern Generation) tools; a process that occurs during manufacturing preparation. The fact that Al-Asaad does not repeatedly state “these patterns were made at the factory” is irrelevant; it is implicit in the nature of deterministic BIST that the vectors are predetermined and stored. Narayanan provides the selected hardware context (test pattern memory) where such vectors would reside. The combination simply applies the known technique of on-line deterministic BIST (Al-Asaad) to the existing selected hardware infrastructure of a multi-core system (Narayanan) to achieve the predictable result of in-field testing.
Second of all, Applicant argued that that neither reference teaches a DMA controller retrieving patterns via an interconnection network. The Examiner respectfully disagrees because this argument improperly elevates nomenclature over function. Al-Asaad teaches a “Test Generator” (TG) that applies deterministic patterns to a circuit under test. Narayanan teaches a “Self-Test Controller” that retrieves patterns from a “Test Pattern Memory” (Fig. 3, element 206) and applies them to scan chains. A PHOSITA would recognize that a controller that fetches data from memory and streams it to selected hardware (scan chains) performs the essential function of a DMA engine. The “interconnection network” is a necessary structural component of any system-on-chip where a controller accesses a memory space; it is implied by the architecture of both references. To argue that a “Self-Test Controller” coupled to a “Test Pattern Memory” does not teach the claimed “DBIST DMA controller” is to ignore the basic principles of digital design, where such a controller necessarily utilizes the system bus (interconnection) to perform direct memory access for performance reasons, especially in the on-line context taught by Al-Asaad where testing is interleaved with functional operation.
Lastly, Applicant argued that that Narayanan only tests during reset and transitions to functional operation after testing, not selectively during functional mode. The Examiner respectfully disagrees. Narayanan provides a system with multiple discrete selected hardware blocks (lockstep cores 102, 104) and the infrastructure to test them via scan chains. Al-Asaad provides the methodology to perform that testing while the system is online. Al-Asaad’s Figure 2 and Section 3.1 explicitly teach overlapping test cycles with normal functional cycles. A PHOSITA seeking to improve the availability of the system in Narayanan (which currently requires a full reset to test) would apply Al-Asaad’s time-multiplexing technique. This would allow one core to be placed in test mode for a few cycles (applying the deterministic patterns) while the other core remains in functional mode, or while other selected hardware blocks outside the lockstep pair continue normal operation. This is not a new invention; it is a straightforward application of a known testing schedule to a known multi-block architecture.
Therefore, the counter-arguments fail because they seek to read the references in isolation and ignore the teaching of the combination. The claimed “computer architecture” is merely the implementation of known on-line deterministic BIST techniques (Al-Asaad) using the existing selected hardware scan and memory infrastructure of a modern system-on-chip (exemplified by Narayanan). The motivation to combine is strong (improving system safety and availability), and the result is predictable. Thus, the prior rejection of the claims is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 7-9, 13, 14, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Narayanan et al (US2020/0309851 A1) (hereinafter D1) and further in view of Al-Assad et al “On-line Built-In Self-Test For Operational Faults”
Claim 1: D1 teaches a computer architecture comprising: a device (e.g. fig. 3) having: a test vector memory (TVM) space (e.g. item 206) configured to store deterministic test patterns (e.g. [0023] -While Narayanan mentions both pre-defined and pseudo-random patterns, the reference inherently supports deterministic patterns as one embodiment); and a deterministic built-in self-test(DBIST) direct memory access (DMA) controller (e.g. item 202) configured to retrieve the deterministic test patterns directly from the TVM space (e.g. self-test controller 202 retrieves test patterns directly from memory 206- [0023]) and apply the deterministic test patterns, using a scan bus, to at least one selected hardware block under test (e.g. controller 202 applies the test patterns to scan chains (e.g. SC1-SCM) within “lockstep cores” (102, 104), which are the “selected hardware blocks under test” - item 102 & item 104 – [0023]-[0024], [0028]-[0030]). Not explicitly taught by D1 is that the test patterns are "generated during manufacturing of the device and stored for use during in-field testing" and applying the test patterns to "at least one selected hardware block under test during the in-field testing, one or more other selected hardware blocks of the device remain in a functional mode".
However, D2 explicitly teaches "on-line periodic BIST" using "deterministic test sequences" for detecting "operational faults" that occur during normal operation in the field . The reference confirms these are the same types of tests applied during manufacturing, reused for on-line testing. Furthermore, D2 teaches that "the test sequence may be partitioned into small sequences that are applied separately" and that testing occurs while the system remains operational . This inherently requires that other selected hardware blocks remain functional during testing of a selected block. Finally, D2's "test generator" performs the function of retrieving and applying deterministic patterns to the circuit under test . In a system-on-chip implementation, such retrieval necessarily occurs via an interconnection network.
Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, to applying D2's on-line deterministic BIST technique to D1's lockstep core architecture in order to improve the safety and availability of the lockstep system taught by D1.
As per claim 13, the claimed features are rejected similarly to claim 1 above.
Claim 2: D1 and Al-Assad et al teach the computer architecture of claim 1, wherein the DBIST DMA controller sends a scan bus signal from the scan bus and a scan clock signal to the at least one selected hardware block under test (e.g. D1- [0029]- see fig. 3).
As per claim 14, the claimed features are rejected similarly to claim 2 above.
Claim 3: D1 and Al-Assad et al teach the computer architecture of claim 2, wherein the scan bus signal provides the deterministic test patterns to the at least one selected hardware block under test (e.g. D1- [0029]).
Claim 7: D1 and Al-Assad et al teach the computer architecture of claim 1, further comprising a multiple input signature register (MISR) configured to receive outputs from the at least one selected hardware block under test during DBIST testing and provide a compacted signature for comparison to an expected signature (e.g. D1: [0024]-[0026]).
As per claim 16, the claimed features are rejected similarly to claim 7 above.
Claim 8: D1 and Al-Assad et al teach the computer architecture of claim 1, wherein DBIST DMA controller applies test patterns to the at least one selected hardware block under test (D1: [0024]-[0029] & [0035]) while maintaining clock signals to downstream selected hardware blocks in a glitch-free manner (e.g. Al-Assad et al: Section II and Section II-B).
Claim 9: D1 and Al-Assad et al teach the computer architecture of claim 1, wherein the deterministic test patterns are generated by a manufacturer of the at least one selected hardware block under test (e.g. D1: [0023]-[0024] “The test pattern may be generated by a built-in test pattern generator or by external automatic-test-equipment (ATE) and stored prior to deployment” & Al-Assad et al: Section III “A deterministic test generator stored a fixed sequence of pre-computed test vectors designed by the circuit manufacturer…”).
As per claim 17, the claimed features are rejected similarly to claim 9 above.
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over D1 and Al-Assad et al teach as applied to claim 1 above, and further in view of Sinha et al (US2022/0120811 A1) (hereinafter D2).
Claim 4: D1 teaches the computer architecture of claim 1, but fails to teach that the device is part of a field-programmable gate array (FPGA). However, such a technique was known in the art, before the effective filing date of the claimed invention, as disclosed by D2 (e.g. [0025]). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the circuit of D1 using an FPGA as taught by D2 because FPGAs are flexible and can be reprogrammed after manufacture, which allows for changes in functionality without needing to redesign or replace the entire device.
Claim(s) 5, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Al-Assad et al as applied to claim 1 above, and further in view of Lin et al (US2008/0034192 A1) (hereinafter D3).
Claim 5: D1 teaches the computer architecture of claim 1, but fails to teach that that the deterministic test patterns are generated at a manufacturing facility and stored in an uncompressed format. However, such a technique was known in the art, before the effective filing date of the claimed invention, ad disclosed by D3 (e.g. [0007] & [0025]). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the device of D1 with the one taught by D3, in order to achieve deterministic initialization of lockstep cores with manufacturing-generated patterns.
Claim 15: D1 and D3 teach the method of claim 13, wherein the device communicates with a system controller communicating with at least one selected hardware block under test via a programmable side channel (e.g. see connection between item 210 and 122- [0103] -D3).
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Al-Assad et al as applied to claim 1 above, and further in view of Thekke Veetil et al (US 2024/0003973 A1).
As per claim 6, D1 teaches the computer architecture of claim 1 but fails to teach a DFx lockout circuit configured to prevent access to at least one selected hardware block under test on a programmable security setting. However, such a technique was known in the art, before the effective filing date of the claimed invention, as disclosed by Thekke Veetil et al (e.g. [0015] [0020]). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the teaching of D1 with the one disclosed by Thekke Veetil et al, in order to prevent tempering during in-field testing, as security is a well-known requirement for safety-critical systems.
Claim(s) 10-12, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Al-Assad et al as applied to claim 1 above, and further in view of Davutoglu et al (US2003/0131327 A1) (hereinafter D4).
Claim 10: D1 teaches the computer architecture of claim 1, but fails to teach that the at least one selected hardware block under test is coupled to a plurality of other selected hardware blocks, and wherein the plurality of other selected hardware blocks remain functional during DBIST testing of the at least one selected hardware block. However, the technique of selecting a circuit among a plurality of circuits for testing was known in the art, before the effective filing date of the claimed invention, as disclosed by D4 (e.g. [0016]). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the teaching of D1 with the one taught by D4 in order to have the capability of selectively testing devices.
As per claim 18, the claimed features are rejected similarly to claim 10 above.
Claim 11: D1 and D4 teach the computer architecture of claim 10, but fail to teach that a system or device controller using firmware allows the plurality of other selected hardware blocks to remain functional during the DBIST testing of the at least one selected hardware block. However, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, that the operations performed by D1 and D4 require firmware or equivalent embedded control logic, which would have been understood by one of ordinary skill in the art as necessarily present even if not explicitly taught.
As per claim 19, the claimed features are rejected similarly to claim 11 above.
Claim 12: D1 and D4 teach the computer architecture of claim 10, but fail to teach output clamping logic allows the plurality of other selected hardware blocks to remain functional during the DBIST testing of the at least one selected hardware block. . However, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to use any known technique to select a specific circuit for testing while preventing other circuits from being testing, because such a modification would have involved since such a modification would have involved the ese of known technique to improve similar devices (methods, or products) in the same way.
As per claim 20, the claimed features are rejected similarly to claim 12 above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 3/9/2026