Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1, 11 and 19
b. Pending: 1-20
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
The position taken in the office action mailed on 10/22/2025 is hereby maintained for the revised rationale set forth below. Previously presented 103 rejection is further reinforced in view of the newly discovered reference Choi (US 20250370935).
Rejections based on the newly cited reference(s) follow.
Drawings
Replacement sheets to Figs. 2, 4 are reviewed and accepted.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-8, 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20250370935).
Regarding independent claim 1, Choi discloses an integrated circuit (IC) device (Figs. 1-5), comprising:
initiator circuitry configured to issue a first transaction that comprises a memory access request and a first target address associated with a first region of memory cells (Fig. 3 shows transaction 140 and [0065] describes that device address may be a device address stored in the address register 112. The device address may be mapped to the physical address of the first memory region 132 of the memory 130);
transaction redundancy circuitry configured to generate a second transaction that comprises the memory access request of the first transaction and a second target address associated with a second region of the memory cells (Fig. 3 and [0065] describes address translator 120 and convert the physical address of the first memory region 132 mapped to the device address into the physical address of the second memory region 134); and
address transformer circuitry configured to transform the second target address of the second transaction to a third target address associated with the second region of the memory cells (Fig. 5 and [0080] describes that device address 560 may be converted into a third physical address that designates the third memory region 136).
Choi doesn’t explicitly show address transformer circuitry, but it does perform all the required functionality. Here examiner asserts that the circuitry is inherently present.
Regarding claim 2, Choi discloses all the elements of claim 1 as above and further the address transformer circuitry is further configured to: determine a codeword based on the second target address; and embed the codeword in the second target address to provide the third target address (Figs. 1-5 and corresponding sections of the specification describes mapping second address into a physical area. That means coding is happening).
Regarding claim 7, Choi discloses all the elements of claim 1 as above and further the transaction redundancy circuitry is further configured to determine the second target address based on the first target address and a fixed offset ([0062] describes applying fixed offset for address translation).
Regarding claim 8, Choi discloses all the elements of claim 1 as above and further the memory access request comprises a write request the first transaction further comprises write data; and the transaction redundancy circuitry is further configured to generate the second transaction to include the write request and the write data (Figs. 1-3 and [0059]).
Regarding claim 10, Choi discloses all the elements of claim 1 as above and further a memory system comprising the memory cells and a memory controller configured to access the memory cells, including to perform the memory access request of the first transaction with respect to the first target address of the first region of the memory cells and to perform the memory access request of the second transaction with respect to the third target address of the second region of the memory cells (Fig. 5 in flowchart describes the prescribed sequence).
Regarding independent claim 19, all the claim limitations are exactly the same as independent claim 1 and henceforth rejected the same way.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20250370935) in view of Xu (CN 103633741).
Regarding claim 5, Choi discloses all the elements of claim 1 as above and through Xu further the address transformer circuitry is further configured to transform the second target address to the third target address based on the second target address and a cyclic redundancy check (CRC) code derived from a generator polynomial on a finite field ([0026] and claim 4 describes using cyclic redundancy check (CRC) code to transform target address).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Xu to modified Choi in order to provide an intelligent substation sampling value network data exchange method and device, which solves the technical problem of reducing the cost of protection device, avoiding delay uncertainty of the network data packet as taught by Xu ([0006]).
Claims 9, 11, 13, 15, 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20250370935) in view Kwok (US 10256842).
Regarding claim 9, Choi discloses all the elements of claim 1 as above and through Kwok further the memory access request comprises a read request, further comprising: redundant transaction management circuitry configured to compare read response data returned from the first region of the memory cells in response to the first transaction, to read response data returned from the second region of the memory cells in response to the second transaction (Claim 1 describes controller is to: compare, in response to a read request, a first codeword associated with the set of redundant codewords to a second codeword selected from the set of redundant codewords to determine whether a section of the first codeword differs from a corresponding section of the second codeword by at least a predefined threshold amount).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Kwok to modified Choi in order to provide with an apparatus comprising a memory to store a set of redundant codewords; and a controller to read data from the memory, wherein the controller is to compare a first codeword associated with the set of redundant codewords to a second codeword associated with the set of redundant codewords to determine whether a section of the first codeword differs from a corresponding section of the second codeword by at least a predefined threshold amount as taught by Kwok ((46)).
Regarding independent claim 11, Kwok teaches a system-on-chip (SoC), (Fig. 1 and (16) describes System-on-a-Chip (SoC)) comprising:
a single-channel memory subsystem comprising memory cells and a memory controller configured to access the memory cells based on memory access requests (Fig. 1 shows the memory subsystem);
Regarding limitation: “initiator circuitry configured to issue a first transaction that comprises a memory access request and a first target address associated with a first region of the memory cells; transaction redundancy circuitry configured to generate a second transaction that comprises the memory access request of the first transaction and a second target address associated with a second region of the memory cells; address transformer circuitry configured to transform the second target address of the second transaction to a third target address associated with the second region of the memory cells; and” is exactly the same as recited in independent claim 1 and henceforth rejected the same way by Choi as before;
Kwok further teaches redundant transaction management circuitry configured to compare read response data returned from the first region of the memory cells in response to the first transaction, to read response data returned from the second region of the memory cells in response to the second transaction (Claim 1 describes controller is to: compare, in response to a read request, a first codeword associated with the set of redundant codewords to a second codeword selected from the set of redundant codewords to determine whether a section of the first codeword differs from a corresponding section of the second codeword by at least a predefined threshold amount).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Kwok to modified Choi in order to provide with an apparatus comprising a memory to store a set of redundant codewords; and a controller to read data from the memory, wherein the controller is to compare a first codeword associated with the set of redundant codewords to a second codeword associated with the set of redundant codewords to determine whether a section of the first codeword differs from a corresponding section of the second codeword by at least a predefined threshold amount as taught by Kwok ((46)).
Claim 13 is exactly the same as claim 2 and henceforth rejected the same way by Choi and Kwok.
Regarding claim 15, Choi and Kwok together disclose all the elements of claim 13 as above and through Choi further address transformer circuitry is further configured to compute the codeword based on the second target address (Figs. 1-5 and corresponding sections of the specification describes mapping second address into a physical area. That means coding is happening).
Regarding claim 17, Choi and Kwok together disclose all the elements of claim 11 as above and through Choi further the transaction redundancy circuitry is further configured to selectively generate the second transaction based on one or more of: the first target address; an identifier associated the first transaction; and a privilege level associated with the initiator circuitry (Figs. 2-3 and corresponding sections of the specification describes transaction 140 as input to address register 112 with the target address).
Regarding claim 18, Choi and Kwok together disclose all the elements of claim 11 as above and through Choi further the address transformer circuitry is further configured to selectively generate the second transaction based on one or more of: the first target address; an identifier associated the first transaction; a privilege level associated with the initiator circuitry; and the second target address (Figs. 2-3 and corresponding sections of the specification describes transaction 140 as input to address register 112 with the target address).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20250370935) in view Kwok (US 10256842) and Xu (CN 103633741).
Regarding claim 14, Choi and Kwok together disclose all the elements of claim 13 as above and through Xu further the codeword is based on one or more of: a Hamming code; an extended Hamming code; and a cyclic redundancy check (CRC) code derived from a generator polynomial on a finite field ([0026] and claim 4 describes using cyclic redundancy check (CRC) code to transform target address).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Xu to modified Choi in order to provide an intelligent substation sampling value network data exchange method and device, which solves the technical problem of reducing the cost of protection device, avoiding delay uncertainty of the network data packet as taught by Xu ([0006]).
Allowable Subject Matter
Claims 3-4, 6, 12, 16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 3/16/2026