Prosecution Insights
Last updated: July 17, 2026
Application No. 18/608,798

DISPLAY APPARATUS

Non-Final OA §102§103
Filed
Mar 18, 2024
Priority
Mar 24, 2023 — RE 10-2023-0039018 +1 more
Examiner
MIHALIOV, DMITRI
Art Unit
4100
Tech Center
4100
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allowance Rate
18 granted / 24 resolved
+15.0% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
24 currently pending
Career history
48
Total Applications
across all art units

Statute-Specific Performance

§103
82.8%
+42.8% vs TC avg
§102
12.5%
-27.5% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 24 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) based on the applications filed in the Republic of Korea on March 24, 2023 and May 18, 2023, and receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. It should be noted that in order to effectively benefit from the foreign priority date, an English translation of the certified copies (of the foreign applications as filed) filed together with statements that the translations of the certified copies are accurate must be presented. Information Disclosure Statement The information disclosure statement (IDS) submitted on March 18, 2024 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Title The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: --Display Apparatus Including Three Different Colored Sub-Pixels Arranged Obliquely-- Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3, 5, 10-13 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Long et al. (U.S. Pub. 2022/0359640), hereinafter Long. Regarding Claim 1, Long teaches a display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) comprising: -a power line ((Vdd) and vias (Vn), e.g. second from right of Fig. 3A as well as (rst1); Fig. 3A, Paragraphs [0087] and [0095]) extending in a first direction (e.g. the lateral of Fig. 3A, hereinafter ‘X-Direction’), and in a second direction perpendicular to the first direction (e.g. the vertical of Fig. 3A, hereinafter ‘Y-Direction’); and -a first sub-pixel having a first pixel electrode ((AD4) of (SP4); Figs. 3A, Paragraph [0105]), a second sub-pixel having a second pixel electrode ((AD3) of (SP3); Figs. 3A, Paragraph [0105]), and a third sub-pixel having a third pixel electrode ((AD2) of (SP2); Figs. 3A, Paragraph [0105]), which display different colors from each other (Paragraphs [0091] and [0105] – in this case the Examiner is taking the embodiment wherein all are different colors), and which are arranged in a third direction crossing both the first direction and the second direction (e.g. a diagonal direction between the vertical and the lateral of Fig. 3A, hereinafter ‘Diagonal’), in a plan view. Examiner notes that the limitation “arranged” may be broadly interpreted such that the arrangement is as seen in Long. Examiner also brings Applicant’s attention to Fig. 5B. Regarding Claim 2, Long teaches a display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 1, wherein: -second pixel electrode (AD3) overlaps a portion of a first capacitor electrode of the first sub-pixel ((Ce1) of (SP4); Figs. 3A and 3D, Paragraph [0089]). Regarding Claim 3, Long teaches a display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 2, wherein: -the first capacitor electrode (Ce1) is electrically connected to a driving gate electrode of the first sub-pixel (‘gate electrode’ of (Td) of (SP4); Fig. 2A, Paragraphs [0089] and [0090]). Regarding Claim 5, Long teaches a display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 1, wherein: -the second pixel electrode (AD3) overlaps a portion of an active layer of the first sub-pixel ((ACTd) of (SP4); Figs. 3A and 3C, Paragraph [0094]). Regarding Claim 10, Long teaches a display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 1, further comprising: -a capacitor-blocking line ((IPB) of, e.g. (SP4); Figs. 3A and 3E, Paragraph [0097]) between a first capacitor electrode of the first sub-pixel ((Ce1) of (SP4); Figs. 3A and 3D, Paragraph [0089]) and a first capacitor electrode of the second sub-pixel ((Ce1) of (SP3). Notably the left side (IPB) of (SP4) (e.g. Figs. 3A and 3E) extends beyond the left side of (Ce1) of (SP4) and is therefore laterally (X-direction) between the two first capacitor electrodes). Regarding Claim 11, Long teaches a display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 10, wherein: -the capacitor-blocking line (IPB) is electrically connected to the power line (e.g. specifically (Vdd)) (Paragraph [0097], see also structure in Fig. 4B). Regarding Claim 12, Long teaches a display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 10, wherein: - the capacitor-blocking line (IPB) is at a same layer (consisting of sublayers (IN) and (ILD); Fig. 4B, Paragraph [0093]) as gate electrodes of the first sub-pixel, the second sub-pixel, and the third sub-pixel ((GL) of (SP4), (SP3), and (SP2), respectively; Figs. 3A and 4B, Paragraph [0095]). Regarding Claim 13, Long teaches a display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 12, wherein: -the power line (Vdd) comprises: a horizontal power line extending in the first direction (portion of (Vdd) expanding in the positive X-Direction, e.g. middle right-shifted segment, including via (v3), see Figs. 3A, 3F, and 4B); and -a vertical power line extending in the second direction (portion of (rst1) in the Y-Direction, e.g. second ‘expanded’ portion shifted in negative Y-Direction, See Figs. 3A, 3E, and 4C), and at a layer under the horizontal power line (specifically (IN) and under the labelled (Vdd) portions, See Figs. 4B and 4C), and wherein the capacitor-blocking line (IPB) is at a same layer as the horizontal power line (specifically (v3), within (ILD)). Examiner notes that reasonable broad interpretations of what constitutes the “powerline” is being utilized in this rejection. This matches the broadness utilized by the Applicant, for example, in that some claim limitations referring to the powerline are directed to Applicant’s (EDLp) (e.g. “the capacitor-blocking line (IPB) is electrically connected to the power line” seems to be directed to Paragraph [0090]) while others towards (ESLh) (e.g. “capacitor-blocking line is at a same layer as the horizontal power line” seems to be directed to Paragraph [0100] and Fig. 7). Regarding Claim 19, Long teaches a display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 1, further comprising: -a data line ((DL), e.g. center (DL) of Fig. 3A; Figs. 3A and 3G, Paragraph [0098]) extending in the second direction (Y-Direction), wherein - the third pixel electrode (AD2) overlaps a portion of the data line (Center (DL)) (See Fig. 3A). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4, 6, 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Long in view of Lee (U.S. Pub. 2020/0144349), hereinafter Lee. Regarding Claim 4, Long teaches the display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 1, but does not explicitly teach: -the first capacitor electrode is at a layer under the driving gate electrode of the first sub-pixel. Lee teaches a display apparatus (comprising an array substrate, Figs. 1-10, Paragraphs [0002] and [0017]), wherein: -the first capacitor electrode ((Cst1); Fig. 9, Paragraph [0066]) is at a layer (within (Gl1); Fig. 9, Paragraph [0097]) under the driving gate electrode of the first sub-pixel ((G1) of driving transistor (T1); Fig. 9, Paragraph [0066])). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee into the device of Long such that the first capacitor electrode is at a layer under the driving gate electrode of the first sub-pixel. This would be due to the fact that doing so would produce the expected result of incorporating an applicable layer structure of a sub-pixel with similar circuit functionality (e.g. the first capacitor electrode electrically connects to the driving gate electrode). Regarding Claim 6, Long teaches the display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 1, wherein: -the first active layer of the first sub-pixel (ACTd) of (SP4) is electrically connected to the first pixel electrode (AD4) (See Fig. 2A, wherein (LE) is the anode of the pixel (Paragraph [0089]). Long does not explicitly teach: -a first active layer of the first sub-pixel partially overlapping a driving gate electrode of the first sub-pixel Lee teaches a display apparatus (comprising an array substrate, Figs. 1-10, Paragraphs [0002] and [0017]), wherein: -a first active layer of the first sub-pixel ((A1) of driving transistor (T1); Fig. 9, Paragraph [0086])) partially overlapping a driving gate electrode of the first sub-pixel ((120), e.g. (120R); Figs. 6 and 9, Paragraph [0080] and [0110]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee into the device of Long such that it includes a first active layer of the first sub-pixel partially overlapping a driving gate electrode of the first sub-pixel. This would be due to the fact that doing so would produce the expected result of incorporating an applicable layer structure of a sub-pixel with similar circuit functionality (e.g. the first active layer of the first sub-pixel is electrically connected to the first pixel electrode). Regarding Claim 14, Long teaches the display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 1, wherein: -a first active layer of the second sub-pixel ((ACTd) of (SP3), specifically the right side of the layer; Figs. 3A and 3C, Paragraph [0094]) is between a first capacitor electrode of the second sub-pixel ((Ce1) of (SP3); Figs. 3A and 3D, Paragraph [0089]) and a first capacitor electrode of the third sub-pixel ((Ce1) of (SP4)). Long does not explicitly teach: -a first active layer of the second sub-pixel partially overlapping a driving gate electrode of the second sub-pixel Lee teaches a display apparatus (comprising an array substrate, Figs. 1-10, Paragraphs [0002] and [0017]), wherein: -a first active layer of the second sub-pixel ((A1) of driving transistor (T1); Fig. 9, Paragraph [0086])) partially overlapping a driving gate electrode of the second sub-pixel ((120), e.g. (120R); Figs. 6 and 9, Paragraph [0080] and [0110]) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Lee into the device of Long such that it includes a first active layer of the second sub-pixel partially overlapping a driving gate electrode of the second sub-pixel. This would be due to the fact that doing so would produce the expected result of incorporating an applicable layer structure of a sub-pixel with similar circuit functionality (e.g. the first active layer of the second sub-pixel is electrically connected to the first pixel electrode, as set by the sub-pixel circuits). Note: this structural incorporation would be applied to all sub-pixels in Long. Regarding Claim 15, Long as modified by Lee teaches the display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 14, wherein: the first active layer of the second sub-pixel (Lee, (A1) which includes (S1) and (D1); Fig. 7 , Paragraph [0086]- as incorporated into (SP3) of Long) comprises a protruding portion extending in the first direction (Lee, e.g. the portion corresponding to (S1) which expands in Y direction, Fig. 7), and wherein the protruding portion extends to a switching gate electrode of the second sub-pixel (Lee, e.g. to (G2) of switching transistor (T2); Fig. 7, Paragraph [0067]). Regarding Claim 16, Long as modified by Lee teaches the display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 14, wherein: the third sub-pixel (Modified Long, (SP4)) comprises a first active layer of the third sub-pixel (Lee, (A1) of Modified Long (SP4)) partially overlapping a driving gate electrode of the third sub-pixel (Lee, (G1) of Modified Long (SP4)), and wherein the first active layer of the third sub-pixel ((A1) of (SP4)) is integrally formed with the first active layer of the second sub-pixel ((A1) of (SP3)) (See Paragraphs [0065] and [0095] of Lee, as well as Fig. 3C and Paragraph [0094] of Long). Examiner notes that the limitation “integrally formed” in a device claim is rather broadly interpreted and only has patentable weight in that it distinguishes the structure. In this case, Examiner understands it to mean ‘formed of the same material’, which is true for the active layers in both Long and Lee. Regarding Claim 17, Long as modified by Lee teaches the display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 16, wherein: -the driving gate electrode of the second sub-pixel (Lee, (G1) of Modified Long (SP3), Figs. 6 and 7) and the driving gate electrode of the third sub-pixel (Lee, (G1) of Modified Long (SP4), Figs. 6 and 7) face each other (e.g. on the vertical faces, i.e. laterally facing each other, Fig. 6). Regarding Claim 18, Long as modified by Lee teaches the display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 14, wherein: -the first active layer of the second sub-pixel (Lee, (A1) which includes (S1) and (D1); Fig. 7 , Paragraph [0086]- as incorporated into (SP3) of Long) is electrically connected to the power line (Lee, (7); Figs. 5-7, Paragraph [0066]. See also Long, Figs. 2A and 3A). Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Long in view of Mou et al. (U.S. 2021/0376026), hereinafter Mou. Regarding Claim 8, Long teaches the display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 1, but does not explicitly teach: -the second pixel electrode overlaps a portion of an active layer of the third sub-pixel. Mou teaches a display apparatus (comprising an array substrate (100), Figs. 1A-10C and 12, Paragraphs [0054]), wherein: -the second pixel electrode (electrode (1131) of (110); Fig. 12, Paragraphs [0227]) overlaps a portion of an active layer ((310); Figs. 9A, Paragraph [0171]) of the third sub-pixel (e.g. (130)) (Compare to structural schematic of Figs. 10A and 12, in this case electrode (1131) overlaps a portion of active layers for all three sub-pixels). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Mou into the device of Long such that the second pixel electrode overlaps a portion of an active layer of the third sub-pixel. Futhermore, the incorporation would be done such that B. This would be due to the fact that doing so would improve brightness and better ensure right arrangement of pixels (Mou, Paragraphs [0052] and [0056]). Regarding Claim 9, Long as modified by Mou teaches the display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 8, wherein: -a portion of the active layer of the third sub-pixel (Long, (ACTd) of (SP4); Figs. 2A, 3A, 3C) is electrically connected to the third pixel electrode (AD4) (See Fig. 2A, wherein (LE) is the anode of the pixel (Paragraph [0089]). Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Long in view of Kim et al. (U.S. 2021/0376026), hereinafter Kim. Regarding Claim 20, Long teaches the display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 1, but does not explicitly teach: - a first color conversion unit in the first pixel electrode, and overlapping the first pixel electrode; -a second color conversion unit in the second pixel electrode, and overlapping the second pixel electrode; and -a third color conversion unit in the third pixel electrode, and overlapping the third pixel electrode. Kim teaches a display apparatus ((1), Figs. 1-13, Paragraph [0056]), wherein: -a first color conversion unit ((TPL); Fig. 3, Paragraph [0058]) in the first pixel electrode, and overlapping the first pixel electrode ((PXE) of leftmost emission area (EMA); Fig. 3, Paragraph [0063]); (corresponding to blue) -a second color conversion unit ((WCL1); Fig. 3, Paragraph [0058]) in the second pixel electrode, and overlapping the second pixel electrode ((PXE) of the center emission area (EMA)); (corresponding to green) and -a third color conversion unit ((WCL2); Fig. 3) in the third pixel electrode, and overlapping the third pixel electrode ((PXE) of the rightmost emission area (EMA); Fig. 3). (corresponding to red) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kim into the device of Long such that it further comprises a first color conversion unit in the first pixel electrode, and overlapping the first pixel electrode; a second color conversion unit in the second pixel electrode, and overlapping the second pixel electrode; and a third color conversion unit in the third pixel electrode, and overlapping the third pixel electrode. This would be due to the fact that doing so would allow multiple colors to be displayed from a common emission wavelength of sub-pixel electrodes (Kim, Paragraph [0072]) and improving display quality (Kim, Paragraph [0167]). Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Long in view of Lee, and in further view of Shim et al. (U.S. 2019/0172884), hereinafter Shim. Regarding Claim 7, Long as modified by Lee teaches the display apparatus (comprising an array substrate, Figs. 1-5B, Paragraphs [0033] and [0182]) of Claim 6, comprising: -a first capacitor electrode of the first sub-pixel (e.g. Lee, (Cst1); Fig. 9, Paragraph [0066]) Neither explicitly teaches: -a first capacitor electrode of the first sub-pixel is at a lower layer under the first active layer of the first sub-pixel to overlap the first active layer of the first sub-pixel. Shim teaches a display apparatus ((100); Figs. 1-3, Paragraph [0045]) comprising sub-pixels ((SP), Fig. 1, Paragraph [0045]) wherein: -a first capacitor electrode of the first sub-pixel ((131) Figs. 2 and 3, Paragraph [0066]) is at a lower layer under the first active layer of the first sub-pixel ((121b); Figs. 2 and 3, Paragraph [0068]) to overlap (Figs. 2 and 3, Paragraph [0070]) the first active layer of the first sub-pixel (121b). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Shim into the device of Long as modified by Lee such that a first capacitor electrode of the first sub-pixel is at a lower layer under the first active layer of the first sub-pixel to overlap the first active layer of the first sub-pixel. This would be due to the fact that doing so would increase reliability by allowing the first capacitor electrode to act as a light shielding layer (Shim, Paragraph [0068]). Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DMITRI MIHALIOV/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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Prosecution Timeline

Mar 18, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
99%
With Interview (+33.3%)
3y 5m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
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