DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 08/06/2026 has been accepted and entered. Claims 1-20 remain pending in this application. Applicant’s amendments to the Specification have overcome each and every objection previously set forth in the Non-Final Office Action mailed on 05/06/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20240047513 A1-Su13) in view of Lee et al. (US20220165721A1-Lee21).
Regarding claim 1, Su13 discloses a semiconductor structure (Abstract L1-2), comprising:
a semiconductor substrate (Semiconductor Substrate 102-Examiner's annotated Fig 1O);
a first capacitor disposed over the semiconductor substrate (First/ bottom capacitor 106 over semiconductor substrate 102- Examiner's annotated Fig 1O);
a first conductive via disposed over the first capacitor (First/ bottom conductive via 174 disposed over first capacitor 106-Examiner's annotated Fig 1O-Examiner's annotated Fig 1O);
a second conductive via bonded to the first conductive via (Second/middle conductive via 174 bonded to first/ bottom conductive via 174-Fig 1K, Examiner's annotated Fig 1O);
a second capacitor disposed over the second conductive via (Second conductive via 118 bonded to first conductive via 134D-Fig 1K, Examiner's annotated Fig 1O); and
a first conductive pad (First conductive pad 192-1 over second capacitor 106, coupled to second capacitor-Examiner's annotated Fig 1O) and
a second conductive pad disposed over the second capacitor (Second conductive pad 192-3 over second capacitor 106, coupled to first capacitor 106-Examiner's annotated Fig 1O) and
electrically coupled to the first capacitor and the second capacitor (First/Second conductive pad 192-1/192-3 over second capacitor 106, coupled to first/second capacitors 106 through 190-1-Examiner's annotated Fig 1O, [0049], [0052]).
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Su13 does not disclose a semiconductor structure comprising:
a first dielectric layer completely disposed over a top surface of the semiconductor substrate,
wherein the first capacitor is completely embedded in the first dielectric layer.
Lee21 teaches a semiconductor structure comprising:
a first dielectric layer completely disposed over a top surface of the semiconductor substrate (first dielectric layer IMD3 completely disposed over a top surface of the semiconductor substrate 20-Fig 3),
wherein the first capacitor is completely embedded in the first dielectric layer (first/Left capacitor CAP being completely embedded in the first dielectric layer IMD3-Fig 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Su13, as taught by Lee21 for the purpose of reducing power noise (Lee21: [0151]).
Regarding claim 2, Su13 and Lee21 combination discloses all the elements of claim 1, as noted above.
Su13 further discloses a semiconductor structure (Abstract L1-2), comprising:
a first metal layer disposed over the second capacitor and
electrically coupled to the first conductive pad (First metal layer 176 over second capacitor 106, coupled to First conductive pad 192-1 through 192-2-Examiner's annotated Fig 1O); and
a second metal layer disposed between the second capacitor and the second conductive via (Second metal layer/ flat end of 110a of capacitor 106 disposed between second capacitor 106, and Second/ middle conductive via 174-Examiner's annotated Fig 1O) and
electrically coupled to the second conductive pad (Second metal layer/ flat end of 110a of capacitor 106 disposed between second capacitor 106, and Second conductive via 174, electrically coupled to Second conductive pad 170 through indicated path-Examiner's annotated Fig 1O).
Regarding claim 3, Su13 and Lee21 combination discloses all the elements of claim 2, as noted above.
Su13 further discloses a semiconductor structure (Abstract L1-2), comprising:
a third conductive via electrically coupling the first metal layer to the first conductive pad (Third/ top conductive via 174 electrically connecting first metal layer 176 to First conductive pad 192-1 through indicated path-Examiner's annotated Fig 1O); and
a fourth conductive via electrically coupling the second metal layer to the second conductive pad (Fourth conductive via 118A electrically connecting Second metal layer/ flat end of 110a of capacitor 106 to Second conductive pad flat end of 110a of capacitor 106 through indicated path-Examiner's annotated Fig 1O).
Regarding claim 4, Su13 and Lee21 combination discloses all the elements of claim 3, as noted above.
Su13 further discloses a semiconductor structure (Abstract L1-2), comprising:
wherein a length of the fourth conductive via is greater than a length of the third conductive via in a direction vertical to a top surface of the semiconductor substrate (Fourth conductive via 118 A length being greater than Third/ top conductive via 174 length in a vertical direction to a top of the substrate 102-Examiner's annotated Fig 1O).
Regarding claim 5, Su13 and Lee21 combination discloses all the elements of claim 3, as noted above.
Su13 further discloses a semiconductor structure (Abstract L1-2), comprising:
wherein the third conductive via and the fourth conductive via are disposed on opposite sides of the second capacitor (Fourth conductive via 118 A length being greater than Third conductive via 174 length with Fourth conductive via 118 A and Third conductive via 17 being on opposite side of second/ top capacitor 106-Examiner's annotated Fig 1O).
Regarding claim 6, Su13 and Lee21 combination discloses all the elements of claim 1, as noted above.
Su13 further discloses a semiconductor structure
wherein the first capacitor vertically overlaps the second capacitor (First/ bottom capacitor 106 and Second/ top capacitor 106 vertically overlapped-Examiner's annotated Fig 1O).
Regarding claim 7, Su13 and Lee21 combination discloses all the elements of claim 1, as noted above.
Su13 further discloses a semiconductor structure
Wherein the first dielectric layer surrounding the first capacitor and the first conductive via (First dielectric 166/168 surrounding first capacitor 106 and First/ bottom conductive via 174 -Examiner's annotated Fig 1O); and the semiconductor structure further comprises
a second dielectric layer surrounding the second capacitor and the second conductive via (second dielectric 166/168 surrounding second capacitor 106 and second/ middle conductive via 174-Examiner's annotated Fig 1O) and
bonded to the first dielectric layer (first and second dielectric layers 168/166 bonded-Fig 1K, [0052] L3-7).
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20240047513 A1-Su13) in view of Lee et al. (US20220165721A1-Lee21).
Regarding claim 1, Su13 discloses a semiconductor structure (Abstract L1-2), comprising:
a semiconductor substrate (Semiconductor Substrate 102-
Examiner's annotated Fig 7);
a first capacitor disposed over the semiconductor substrate (First/ bottom capacitor 106 over semiconductor substrate 102- Examiner's annotated Fig 7);
a first conductive via disposed over the first capacitor (Second/ top capacitor 106 disposed over the second conductive via 118-Examiner's annotated Fig 7);
a second conductive via bonded to the first conductive via (First conductive via 118 disposed over first capacitor 106-Examiner's annotated Fig 7);
a second capacitor disposed over the second conductive via (Second conductive via 118 bonded to first conductive via 134D-Fig 1K, Examiner's annotated Fig 7); and
a first conductive pad (First conductive pad 192-2 over second capacitor 106, coupled to second capacitor-Examiner's annotated Fig 7) and
a second conductive pad disposed over the second capacitor (Second conductive pad 194 over second capacitor 106, coupled to first capacitor 106-Examiner's annotated Fig 7) and
electrically coupled to the first capacitor and the second capacitor (First/Second conductive pad 192-2/194 over second capacitor 106, coupled to first/second capacitors 106 through 190-2 along indicated path-Examiner's annotated Fig 7, [0049], [0052]).
Su13 does not disclose a semiconductor structure comprising:
a first dielectric layer completely disposed over a top surface of the semiconductor substrate,
wherein the first capacitor is completely embedded in the first dielectric layer.
Lee21 teaches a semiconductor structure comprising:
a first dielectric layer completely disposed over a top surface of the semiconductor substrate (first dielectric layer IMD3 completely disposed over a top surface of the semiconductor substrate 20-Fig 3),
wherein the first capacitor is completely embedded in the first dielectric layer (first/Left capacitor CAP being completely embedded in the first dielectric layer IMD3-Fig 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Su13, as taught by Lee21 for the purpose of reducing power noise (Lee21: [0151]).
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Regarding claim 8, Su13 and Lee21 combination discloses all the elements of claim 1, as noted above.
Su13 further discloses a semiconductor structure further comprising:
a plurality of conductive connectors disposed over the first conductive pad and the second conductive pad (Conductive connectors 198 disposed over first conductive pad 192-2 and second conductive pad 194 and electrically coupled to first/ second capacitors through indicated path-Examiner's annotated Fig 7) and
electrically coupled to the first capacitor and the second capacitor (Conductive connectors 198 disposed over first conductive pad 192-2 and second conductive pad 194 and electrically coupled to first/ second capacitors through indicated path-Examiner's annotated Fig 7),
wherein the conductive connectors comprise microbumps, wire bonds, copper pillar bumps, or a combination thereof (Conductive connectors 198 comprising a solder ball, a controlled collapse chip connection (C4) bump, a ball grid array (BGA) ball, a micro bump, a copper pillar, or the like, or a combination thereof-[0053] L 43-46).
Claim(s) 9-13, 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20240047513 A1-Su13) in view of Lee et al. (US20220165721A1-Lee21).
Regarding claim 9, Su13 discloses a semiconductor structure (Abstract L1-2), comprising:
a semiconductor substrate (Semiconductor Substrate 102-Examiner's annotated Fig 1O BIS);
a first metal layer disposed over the semiconductor substrate (First metal layer 192-1 over Substrate 102-Examiner's annotated Fig 1O BIS);
a first capacitor disposed over the first metal layer (First/ bottom capacitor 106 over first metal layer 192-1- Examiner's annotated Fig 1O BIS);
a second metal layer disposed over the first capacitor (Second/ bottom metal layer 170 over first/ bottom capacitor 106-Examiner's annotated Fig 1O BIS);
a third metal layer disposed over the second metal layer (Third/ top metal layer 170 over second/ bottom metal layer 170-Examiner's annotated Fig 1O BIS) and
electrically coupled to the second metal layer (Third/ top metal layer 170 over second/ bottom metal layer 170, electrically coupled to second/ bottom metal layer 170 through indicated path-Examiner's annotated Fig 1O BIS);
a second capacitor disposed over the third metal layer (Second/ top capacitor 106 disposed over third/ top metal layer 170) and
vertically overlapping the first capacitor (First/ bottom capacitor 106 and Second/ top capacitor 106 vertically overlapped-Examiner's annotated Fig 1O BIS); and
a fourth metal layer disposed over the second capacitor (Fourth metal layer 192-2 over Second/ top capacitor 106-Examiner's annotated Fig 1O BIS) and
electrically coupled to the first metal layer (Fourth metal layer 192-2 over Second/ top capacitor 106, electrically coupled to First metal layer 192-1 through indicated path-[0052], Examiner's annotated Fig 1O BIS).
Su13 does not disclose a semiconductor structure comprising:
a first dielectric layer completely disposed over a top surface of the semiconductor substrate,
wherein the first capacitor is completely embedded in the first dielectric layer.
Lee21 teaches a semiconductor structure comprising:
a first dielectric layer completely disposed over a top surface of the semiconductor substrate (first dielectric layer IMD3 completely disposed over a top surface of the semiconductor substrate 20-Fig 3),
wherein the first capacitor is completely embedded in the first dielectric layer (first/Left capacitor CAP being completely embedded in the first dielectric layer IMD3-Fig 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Su13, as taught by Lee21 for the purpose of reducing power noise (Lee21: [0151]).
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Regarding claim 10, Su13 and Lee21 combination discloses all the elements of claim 9, as noted above.
Su13 further discloses a semiconductor structure
a first conductive via electrically coupling the first metal layer to the fourth metal layer (First conductive via 190-1 +118 electrically coupling first metal layer 192-1 to Fourth metal layer 192-2 through indicated path-[0052], Examiner's annotated Fig 1O BIS); and
a second conductive via electrically coupling the second metal layer to the third metal layer (Second conductive via 174/176 electrically coupling Second/ bottom metal layer 170 to Fourth metal Third/ top metal layer 170 through indicated path-[0052], Examiner's annotated Fig 1O BIS).
Regarding claim 11, Su13 and Lee21 combination discloses all the elements of claim 10, as noted above.
Su13 further discloses a semiconductor structure
wherein a length of the first conductive via is greater than a length of the second conductive via in a direction vertical to a top surface of the semiconductor substrate ( The length of the first conductive via 190-1+118 is greater than the length of the second conductive via 174/176 in a direction vertical to a top surface of the semiconductor substrate 102-Examiner's annotated Fig 1O BIS).
Regarding claim 12, Su13 and Lee21 combination discloses all the elements of claim 10, as noted above.
Su13 further discloses a semiconductor structure
wherein the second capacitor vertically overlaps the second conductive via (Second/ top capacitor 106 and Second/ bottom metal layer 170 vertically overlapped as showed with the dashed rectangle-Examiner's annotated Fig 1O BIS).
Regarding claim 13, Su13 and Lee21 combination discloses all the elements of claim 10, as noted above.
Su13 further discloses a semiconductor structure
wherein a first width of a middle portion of the first conductive via is greater than a second width of a top portion of the first conductive via (width of portion 190-1 of first conductive via 190-1+118 being greater than width of portion 118-Examiner's annotated Fig 1O BIS) .
Regarding claim 16, Su13 and Lee21 combination discloses all the elements of claim 9, as noted above.
Su13 further discloses a semiconductor structure
a hybrid-bonding structure disposed between the second metal layer and the third metal layer (Hybrid-bonding structure between the second/ bottom metal layer 170 and third/ top metal layer 170-Examiner's annotated Fig 1O BIS, Fig 1K, Fig 1L, [0045] L4-8).
Regarding claim 17, Su13 discloses a semiconductor structure (Abstract L1-2), comprising:
a semiconductor substrate (Semiconductor Substrate 102-Examiner's annotated Fig 1K);
a first capacitor disposed over the semiconductor substrate (First/ bottom capacitor 106 over semiconductor substrate 102- Examiner's annotated Fig 1K)
a second capacitor disposed over and vertically overlapping the first capacitor (First/ bottom capacitor 106 over First over First/ bottom capacitor 106-Examiner's annotated Fig 1K); and
a hybrid-bonding structure disposed between the first capacitor and the second capacitor (Hybrid-bonding structure between Second/ top capacitor 106 and First/ bottom capacitor 106 indicated by a dashed line-Examiner's annotated Fig 1K) and
electrically coupling the first capacitor to the second capacitor (Fig 1L, Second/ top capacitor 106, electrically coupled to First/ bottom capacitor 106 through indicated path-Examiner's annotated Fig 1K, [0045] L4-8).
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Su13 does not disclose a semiconductor structure
Wherein the hybrid-bonding structure comprises
a first dielectric layer completely disposed over a top surface of the semiconductor substrate,
wherein the first capacitor is completely embedded in the first dielectric layer.
Lee21 teaches a semiconductor structure
Wherein the hybrid-bonding structure (PDN/PDC-Fig 3) comprises
a first dielectric layer completely disposed over a top surface of the semiconductor substrate (first dielectric layer IMD3 completely disposed over a top surface of the semiconductor substrate 20-Fig 3),
wherein the first capacitor is completely embedded in the first dielectric layer (first/Left capacitor CAP being completely embedded in the first dielectric layer IMD3-Fig 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Su13, as taught by Lee21 for the purpose of reducing power noise (Lee21: [0151]).
Regarding claim 18, Su13 and Lee21 combination discloses all the elements of claim 17, as noted above.
Su13 further discloses a semiconductor structure
wherein the hybrid-bonding structure (Hybrid-bonding structure between Second/ top capacitor 106 and First/ bottom capacitor 106 showed with the dashed rectangle-Examiner's annotated Fig 1K) comprises:
a first conductive via disposed over the first capacitor (First/ bottom conductive via 174+176 over First/ bottom capacitor 106-Examiner's annotated Fig 1K);
a first dielectric layer surrounding the first conductive via (First/ bottom dielectric layer 168/166 surrounding first/ bottom conductive via 174+176-Examiner's annotated Fig 1K);
a second conductive via disposed below the second capacitor (Second/ top conductive via 174+176 below Second/ top capacitor 106-Examiner's annotated Fig 1K); and
a second dielectric layer surrounding the second conductive via (Second/ top dielectric layer 168/166 surrounding Second/ top conductive via 174+176-Examiner's annotated Fig 1K).
Regarding claim 19, Su13 and Lee21 combination discloses all the elements of claim 18, as noted above.
Su13 further discloses a semiconductor structure
wherein the first conductive via has a first width decreasing in a direction toward the semiconductor substrate (Second/ top conductive via 174+176 below Second/ top capacitor 106, having a second width decreasing from 176 width to 174 width going toward the semiconductor substrate 102-Examiner's annotated Fig 1K), and
the second conductive via has a second width increasing in the direction toward the semiconductor substrate (Second/ top conductive via 174+176 below Second/ top capacitor 106, having a second width increasing from 174 width to 176 width going toward the semiconductor substrate 102-Examiner's annotated Fig 1K).
Regarding claim 20, Su13 and Lee21 combination discloses all the elements of claim 17, as noted above.
Su13 further discloses a semiconductor structure
wherein the hybrid-bonding structure comprises:
a first conductive via adjacent to the first capacitor (First/ bottom conductive via 174+176 adjacent and over First/ bottom capacitor 106-Examiner's annotated Fig 1K);
a first dielectric layer surrounding the first conductive via and the first capacitor (First/ bottom dielectric layer 166/168 surrounding first/ bottom conductive via 174+176 and capacitor 106-Examiner's annotated Fig 1K);
a second conductive via adjacent to the second capacitor (Second/ top conductive via 174+176 adjacent and below Second/ top capacitor 106-Examiner's annotated Fig 1K); and
a second dielectric layer surrounding the second conductive via and the second capacitor (Second/ top dielectric layer 166/168 surrounding Second/ top conductive via 174+176 and capacitor 106-Examiner's annotated Fig 1K).
Claim(s) 9 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20240047513 A1-Su13) in view of Lee et al. (US20220165721A1-Lee21).
Regarding claim 9, Su13 discloses a semiconductor structure (Abstract L1-2), comprising:
a semiconductor substrate (Semiconductor Substrate 102-Examiner's annotated Fig 1O BIS);
a first metal layer disposed over the semiconductor substrate (First metal layer 192-1 over Substrate 102-Examiner's annotated Fig 1O TER);
a first capacitor disposed over the first metal layer (First/ bottom capacitor 106 over first metal layer 192-1- Examiner's annotated Fig 1O TER);
a second metal layer disposed over the first capacitor (Second/ bottom metal layer 170 over first/ bottom capacitor 106-Examiner's annotated Fig 1O TER);
a third metal layer disposed over the second metal layer (Third/ top metal layer 170 over second/ bottom metal layer 170-Examiner's annotated Fig 1O TER) and
electrically coupled to the second metal layer (Third/ top metal layer 170 over second/ bottom metal layer 170, electrically coupled to second/ bottom metal layer 170 through indicated path-Examiner's annotated Fig 1O TER);
a second capacitor disposed over the third metal layer (Second/ top capacitor 106 disposed over third/ top metal layer 170-Examiner's annotated Fig 1O TER) and
vertically overlapping the first capacitor (First/ bottom capacitor 106 and Second/ top capacitor 106 vertically overlapped-Examiner's annotated Fig 1O TER); and
a fourth metal layer disposed over the second capacitor (Fourth metal layer 192-2 over Second/ top capacitor 106-Examiner's annotated Fig 1O TER) and
electrically coupled to the first metal layer (Fourth metal layer 192-2 over Second/ top capacitor 106, electrically coupled to First metal layer 192-1 through indicated path-[0052], Examiner's annotated Fig 1O TER).
Su13 does not disclose a semiconductor structure comprising:
a first dielectric layer completely disposed over a top surface of the semiconductor substrate,
wherein the first capacitor is completely embedded in the first dielectric layer.
Lee21 teaches a semiconductor structure comprising:
a first dielectric layer completely disposed over a top surface of the semiconductor substrate (first dielectric layer IMD3 completely disposed over a top surface of the semiconductor substrate 20-Fig 3),
wherein the first capacitor is completely embedded in the first dielectric layer (first/Left capacitor CAP being completely embedded in the first dielectric layer IMD3-Fig 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Su13, as taught by Lee21 for the purpose of reducing power noise (Lee21: [0151]).
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Regarding claim 14, Su13 and Lee21 combination discloses all the elements of claim 9, as noted above.
Su13 further discloses a semiconductor structure
a first conductive via electrically coupled to the fourth metal layer First conductive via 174 electrically coupled to Fourth metal layer 192-2 through indicated path-Examiner's annotated Fig 1O TER); and
a second conductive via electrically coupled to the third metal layer (Second conductive via (190-1+118) electrically coupling to Fourth metal Third/ top metal layer 170 through indicated path-Examiner's annotated Fig 1O TER).
Regarding claim 15, Su13 and Lee21 combination discloses all the elements of claim 14, as noted above.
Su13 further discloses a semiconductor structure
wherein a length of the second conductive via is greater than a total length of the first conductive via and the second capacitor in a direction vertical to a top surface of the semiconductor substrate (Second conductive via (190-1+118) vertical length being greater than the total vertical length of First conductive via 174/176 and second/ top capacitor 106-Examiner's annotated Fig 1O TER).
Response to Arguments
Applicant’s arguments see pages 8-27 of Remarks, filed on 08/06/2026 with respect to the 35 U.S.C 102 rejection of claims 1-20 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Claims 1, 9, and 17 have been amended to further define the claimed subject matter see pages 3-7 of Amendments to Claims, filed on 08/06/2026.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20240047513 A1-Su13) in view of Lee et al. (US20220165721A1-Lee21), as noted above.
Therefore, claim(s) 1-20 stand rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20240047513 A1-Su13) in view of Lee et al. (US20220165721A1-Lee21).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 09/09/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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