INTERCONNECT STRUCTURE AND METHODS THEREOF

Application No. 18/609,456

• Filed: Mar 19, 2024
• Examiner: RAHMAN, MOHAMMAD A
• Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
• OA Round: 1 (Non-Final)

Office Action

Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/ Restrictions
Applicant's election of group I without traverse: claims 1-17, cancellation of claims 18-20 and submission of new claims 21-23 in the “Response to Election / Restriction Filed - 05/28/2026” is/are acknowledged. This office action considers claims 1-17 and 21-23, in “Claims - 05/28/2026”, pending for prosecution.
Claim Objections
Claims 21-23 objected to because of the following informalities:
Claim 21 recites:
“wherein after depositing the second metal layer a doped ILD layer portion interposes the doped barrier layer and the patterned ILD layer or a doping material layer interposes the second metal layer and the doped barrier layer”. Applicant may recite the following to overcome this objection:
“wherein after depositing the second metal layer, a doped ILD layer portion interposes the doped barrier layer and the patterned ILD layer or a doping material layer interposes the second metal layer and the doped barrier layer”.
Claims 22-23 depend from claim 21.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;

Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.

Claims 1-2, 4, 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiu et al. (US 20230352395 A1 – hereinafter Chiu).
Regarding Claim 1, Chiu teaches a method of fabricating a semiconductor device (see the entire document; Fig. 1A-1L; specifically, ([0038] - [0049]), and as cited below), comprising:
forming a first metal interconnect layer (120 – Fig. 1B – [0026]);
depositing a dielectric layer (132b – Fig. 1I - [0038]) over the first metal interconnect layer (120);
patterning the dielectric layer (132b – Fig. 1J) to form an opening (140 – [0044]) that exposes the first metal interconnect layer (120);
forming a doped barrier layer or a hybrid barrier layer (142 – Fig. 1K – [0045] – WTi is a hybrid layer) along sidewalls and a bottom surface of the opening (140); and
depositing a metal layer (146 – Fig. 1L – [0049]) over the doped barrier layer or the hybrid barrier layer (142).
Regarding Claim 2, Chiu teaches the method of claim 1, further comprising: prior to depositing the metal layer (146), forming a liner layer (144 – [0047] – Fig. 1K) over the doped barrier layer or the hybrid barrier layer (142); and depositing the metal layer (146) over the liner layer (144).
Regarding Claim 4, Chiu teaches the method of claim 1, wherein the forming the doped barrier layer or the hybrid barrier layer includes forming the hybrid barrier layer (142 – WTi) along the sidewalls and the bottom surface of the opening (Fig. 1K).

Claim 11 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsueh et al. (US 20230290678 A1 – hereinafter Hsueh).
Regarding Claim 11, Hsueh teaches a method of fabricating a semiconductor device (see the entire document; Fig. 5; specifically, ([0025] - [0046]), and as cited below), comprising:
forming a first level of a multi-level interconnect network (108 – Fig. 5 – [0025]), wherein the first level of the multi-level interconnect network (108) includes a first via portion (210 – Fig. 5 – [0029]) and a first metal line portion (212 – [0028]); and
forming a second level of the multi-level interconnect network (504 – [0046]) over the first level of the multi-level interconnect network (108), wherein the second level of the multi-level interconnect network (504) includes a second via portion (510 – [0046]) and a second metal line portion (512 – [0046]);
wherein the first level of the multi-level interconnect network includes a first barrier layer configuration (208) at least partially surrounding the first via portion (210) and the first metal line portion (212); and
wherein the second level of the multi-level interconnect network (504) includes a second barrier layer configuration (508 – [0046]), different than the first barrier layer configuration (208), at least partially surrounding the second via portion (510) and the second metal line portion (512).
Allowable Subject Matter
Claims 3, 5-10, 12-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 3: The method of claim 1, wherein the forming the doped barrier layer or the hybrid barrier layer includes forming the doped barrier layer along the sidewalls and the bottom surface of the opening.
Claims 5-9 depend from claim 3.
Regarding claim 10: The method of claim 4, wherein after forming the hybrid barrier layer, performing a bombardment of the hybrid barrier layer using metals, metal alloys, carbides, or nitrides.
Regarding claim 12: The method of claim 11, wherein the first barrier layer configuration includes one of: (i) a doped barrier layer and a liner layer disposed over the doped barrier layer; (ii) the doped barrier layer without the liner layer; (iii) a hybrid barrier layer and the liner layer disposed over the hybrid barrier layer; and (iv) the hybrid barrier layer without the liner layer.
Claims 13-17 depend from claim 12.
REASON FOR ALLOWANCE
Claims 21-23 are allowed over prior art.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 21, the reference(s) of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge do(es) not teach or render obvious, at least to the skilled artisan, the instant invention regarding a method in their entirety (the individual limitations may be found just not in combination with proper motivation).
The most relevant prior art reference(s) (US 20230352395 A1 to Chiu) substantially teach(es) some of limitations in claim 21 as indicated in the rejections of claim 1, but not the limitations of “wherein after depositing the second metal layer a doped ILD layer portion interposes the doped barrier layer and the patterned ILD layer or a doping material layer interposes the second metal layer and the doped barrier layer” as recited in claim 21. Therefore, the claim 21 is deemed patentable over the prior art.
Regarding claims 22-23, they are allowed due to their dependencies on claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is [phone] and email is [e-mail]. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on [phone]. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898

Prosecution Timeline

• Mar 19, 2024: Application Filed
• Jun 26, 2026: Non-Final Rejection mailed — §102, §112 (current)