Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species I in the reply filed on 7/13/2024 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 5/30/2024, 9/30/2024, and 4/28/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20210375857 A1) in view of Lee (US 11489063 B2).
Regarding claim 1, Huang teaches, a method of forming a semiconductor device, the method comprising: having a semiconductor substrate comprising a “source-region recess” (FIG. 8B, source/drain region) 122r below a top surface of the semiconductor substrate 110 and a superlattice structure (“semiconductor stack” 120, paragraph [0013] states “the GAA devices may have one or more channel regions (e.g., nanowires) associated with a single, contiguous gate structure, or multiple gate structures,” the examiner notes that the use of the word “nanowires” indicates that the lattice structure is on the nanometer scale) formed on the top surface of the semiconductor substrate (see FIG. 2), the source/drain region comprising a silicon germanium (SiGe) layer (“sacrificial epitaxial plug” 220 in which [0034] states “for example, the substrate 110 is Si and the sacrificial epitaxial plug 220 is SiGe”) that fills the source/drain region (see FIG. 9B) and a capping layer on the silicon germanium (SiGe) layer (“bottom epitaxial structures” 230, see FIG. 11C), the superlattice structure comprising -a plurality of first layers of a first material (“first semiconductor layers” 122) and a corresponding plurality of second layers of a second material (“second semiconductor layers” 124, further, paragraph [0017] states “first semiconductor layers 122 and the second semiconductor layers 124 are made of materials having different lattice constants”) alternatingly arranged in a plurality of stacked pairs (see above and FIG. 2).
Huang further teaches flipping the semiconductor substrate to expose a backside surface of the semiconductor substrate ([0050] describes a flipping “upside down” of the structure in-between FIGs 13 and 14A, also see the arrow at the top of FIG. 14A indicating a flipping step); etching to remove the capping layer and the silicon germanium (SiGe) layer and form an opening within the source/drain region on the backside surface ([0057] states: “the sacrificial epitaxial structure 320 and the sacrificial epitaxial plug 220 are removed such that an opening 332 is formed between the isolation materials 330 and between the isolation structures 130,” see FIG. 18C showing opening 332 within source/drain region); depositing a metal silicide layer on a top surface of the opening (see FIG. 19B and [0061]: “At least one backside metal alloy layer 350 is formed above the etched top epitaxial structure 240. The backside metal alloy layer 350, which may be silicide layers . . .”); depositing a barrier layer along the opening of the source/drain region on the backside surface and on the metal silicide layer ([0059] states: “A backside CESL 340 is conformally formed in the opening 332,” FIG. 19C shows the CESL (barrier layer) formed on the metal silicide layer); and depositing a metal material on the barrier layer to fill the opening and to form a backside contact ([0062] states: “A backside via 360 is then formed in the opening 332 (see FIGS. 18B) . . . In some embodiments, the backside via 360 may be made of metal . . .”).
Huang does not teach the formation of a first and second liner layer.
Lee teaches, in FIG. 4, a semiconductor device comprising “semiconductor layers” 25 and “second semiconductor layers” 20 alternatingly stacked; in paragraph 16, Lee further teaches “The second semiconductor layers 25 or portions thereof may form nanosheet channel(s) of the GAA FET device. The term nanosheet is used herein to designate any material portion with nanoscale . . . dimensions.” Paragraph 33 teaches “a first liner layer 64 is formed on the end portions of the first semiconductor layers 20 . . . the first liner layer 64 is etched and formed into inner spacers.” (a first liner layer is formed on the substrate, etching a bottom portion of the first liner layer to form an etched first liner layer, also see FIGs 14 and 15), paragraph 34 teaches “a second liner layer 66 is formed on the first liner layer 64 . . . In some embodiments, the second liner layer 66 is conformally epitaxially grown in the S/D trench” (epitaxially growing a second liner layer in the superlattice structure (see FIG. 15) and along the first liner layer). The examiner notes that while the second epitaxial layer is not formed on an already etched first liner layer, paragraph 9 states “The order of the operations/processes [of the method] may be interchangeable.”
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the method taught by Huang such that the method includes forming a first liner layer on the substrate, etching a bottom portion of the first liner layer to form a first etched liner layer, and epitaxially forming a second liner layer on the first etched liner layer, as taught by Lee. One having ordinary skill in the art is motived to form the first liner layer in because “By forming the first liner layer 64, the size of cavities 62 is reduced but not completed filled up, due to the cavity height expanding in previous operation 116, which reserves space for the subsequent deposition of a seed layer,” (Lee, paragraph 33) and to form the second liner layer because “the second liner layer 66 is etched and formed into seeds to facilitate later-on S/D epitaxial growth (Lee, paragraph 34). One is further motivated to etch the first liner layer before the deposition of the second liner layer in order to, for example, achieve a consistent etching of the first liner layer without having to use a second liner layer that has an etch selectivity of zero (or a very low/very high etch selectivity) with the first liner layer.
Regarding claim 2, the above described method inherently reduces contact resistance in a semiconductor device compared to a contact resistance of ta semiconductor device comprising a molybdenum silicide layer alone, as is admitted in the present disclosure (see specification filed 3/19/2024, [00103]: “The method 100 advantageously reduces contact resistance in the semiconductor device 200 compared to a contact resistance of a semiconductor device comprising a molybdenum silicide (MoSi) layer alone”).
Regarding claim 6, Huang further teaches, in [0035]: “semiconductor materials are deposited . . . to form the bottom epitaxial structures 230. The semiconductor materials include a single element semiconductor material, such as germanium (Ge) or silicon (Si).”
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20210375857 A1) in view of Lee (US 11489063 B2) in further view of Cho (US 20200381546 A1).
Regarding claim 4, as explained above, Huang and Lee teach the limitations of claim 3. They do not teach dopant concentrations for the first and second liner layers.
Cho teaches, in FIG. 3, “first semiconductor layer” (first liner layer) 150 and “second semiconductor layer” (second liner layer) 152 formed in the stacked region of a semiconductor device. [0059] states: “The second semiconductor layer 152 may be doped with impurities to have a second impurity concentration higher than the first impurity concentration.”
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Huang and Lee such that the second liner layer has a higher dopant concentration than the first liner layer, as taught by Cho. One having ordinary skill in the art is motivated to do so in because “When etching sources, e.g., etching gas or etchant may contact the first and second semiconductor layers 150 and 152, the second semiconductor layer 152 doped with impurities of a high concentration may be etched faster than the first semiconductor layer 150 doped with impurities of a low concentration,” allowing for greater control in later etching steps.
Regarding claim 5, Cho further teaches, in [0056]: “first semiconductor layer 150 includes silicon doped with n-type impurities. For example, the n-type impurities may include phosphorus (P) or arsenic (As).” [0057] states “first semiconductor layer 150 includes silicon-germanium doped with p-type impurities. For example, the p-type impurities may include boron.” [0060] states: “the second semiconductor layer 152 may include a material (or set of materials) the same as a material (or set of materials) of the first semiconductor layer 150.”
It would have been obvious to one having ordinary skill in the art at the effective filing date to further modify the method taught by Huang and Lee such that each of the first liner layer and the second liner layer comprises silicon (Si) doped with germanium (Ge), silicon (Si) doped with phosphorous (P), or silicon germanium (SiGe) doped with boron (B), as taught by Cho. One having ordinary skill in the art is motivated to do so because, for example, use of Silicon doped with phosphorus in the first liner layer enables the layer to serve as a S/D extension in an NMOS transistor (Cho, [0056]), and SiGe doped with boron allows for the same use in a PMOS transistor (Cho, [0057]). The second region should be made to be the same material as the first in order to ensure no depletion region is created, which would block current, as is well known to one having ordinary skill in the art.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20210375857 A1) in view of Lee (US 11489063 B2) in further view Kao (US 20210367063 A1).
Regarding claim 7, as explained above, Huang and Lee teach the limitations of claim 1. Huang and Lee do not teach the use of a cluster tool
Kao teaches a method for forming a semiconductor device which involves the use of a deposition chamber 203 and a mounting platform 211 (see FIG. 11D), [0051] states: “the deposition chamber 203 and the mounting platform 221 may be part of a cluster tool system (not shown). The cluster tool system may be used in conjunction with an automated handling system in order to position and place the substrate 50 into the deposition chamber 203 prior to the deposition processes, position and hold the substrate 50 during the deposition processes, and remove the substrate 50 from the deposition chamber 203 after the deposition processes.” [0020] further teaches that the manufactured device comprises various components, such as nanostructures, stacks, and a substrate “In some embodiments, the nanostructures 55 and the fins 66 may be formed in the multi-layer stack 64 and the substrate 50, respectively, by etching trenches in the multi-layer stack 64 and the substrate 50.” This shows that the above described cluster tool must be capable of deposition, etching, and handing the substrate.
It would have been obvious to one having ordinary skill in the art at the effective filing date to utilize a cluster tool capable of deposition, etching, and handing (as taught by Kao) to execute the method taught by Huang and Lee. One having ordinary skill in the art is motivated to use a cluster tool in order to decrease manufacturing time, by ensuring that the method can be performed without transportation steps.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ye (US 20180277649 A1) – A “processing system” configured to perform deposition and etching steps as well as movement of substrates.
Song (US 20210119031 A1) – Manufacturing method for wrap-around contacts to reduce S/D resistance, with alternating Si and SiGe nanosheet stack structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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