Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to the requirement for restriction/election filed on 07/06/2026, the applicant elected invention I, method of making. Additionally, applicant canceled claims 11-20 and submitted new claims 21-30. It is noted by the examiner that the new claims do not contain new matter and thus are examined upon the merits below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7, 23 and 26-30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiou et al (US 20220068856).
Chiou et al teaches
[claim 1] A method comprising: bonding a top die over a bottom wafer (figure 2, paragraph 0024, where element 50 is the top die bonded to a bottom wafer [element 70]),
depositing a stress relief layer on the top die and a top surface of the bottom wafer (figure 3, paragraph 0034, where element 108 is the stress-relief layer [labeled buffer layer and stiffener with the function of “stress reduction”], is deposited on the top die [element 50] and top surface of the wafer [to surface of element 70]);
forming a dielectric gap-filling layer on the stress relief layer (figure 4, paragraph 0038, where element 110 is a layer formed on top of the stress relief layer [element 108], and is labeled an encapsulant but also functions as a filler layer [per paragraph 0038] and fills in the gaps, thus acts functionally the same as a dielectric gap-filler layer);
performing a planarization process on the [dielectric gap-filling] layer (figure 4, paragraph 0038, where element 110 is the layer in place of the dielectric gap-filling layer, where a planarization process is performed on said layer);
and sawing the [dielectric gap-filling layer] and the bottom wafer to form a plurality of packages, wherein one of the packages comprises the top die, a portion of the stress relief layer, and a bottom die in the bottom wafer (figure 9, paragraph 0053, where a sawing technique is performed to singulate the die with the wafer, where element 110 is in place of the dielectric gap filled layer, and each package comprises the top die [element 50], a portion of the stress-relief layer [element 108], and a bottom die [element 72 – paragraph 0027 notes that element 72 may have other devices present in the substrate], and the wafer [element 70]).
[claim 7] The method of claim 1, wherein the dielectric gap-filling layer comprises a molding compound, and the molding compound is in physical contact with the stress relief layer (figure 4, paragraph 0042, where element 110 is the dielectric gap-filling layer and is a molding compound and in physical contact with the stress-relief layer [element 108]).
[claim 21] A method comprising: bonding a top die over a bottom die (figure 2, paragraph 0024, where element 50 is the top die bonded to a bottom wafer [element 70], where the wafer contains element 72 which contains a lower die [element 72 – paragraph 0027]);
forming a stress relief layer comprising a first portion contacting a sidewall of the top die and a second portion contacting a top surface of the bottom die (figure 3, paragraph 0034, where element 108 is the stress-relief layer [labeled buffer layer and stiffener with the function of “stress reduction”], is deposited on a sidewall of the top die [element 50], which is the first portion, and a second portion contacting a top surface of the wafer [to surface of element 70]);
and forming a dielectric gap-filling region on the stress relief layer (figure 4, paragraph 0038, where element 110 is a layer formed on top of the stress relief layer [element 108], and is labeled an encapsulant but also functions as a filler layer [per paragraph 0038] and fills in the gaps, thus acts functionally the same as a dielectric gap-filler layer).
[claim 23] The method of claim 21, wherein the dielectric gap-filling region comprises a molding compound in contact with the stress relief layer (figure 4, paragraph 0042, where element 110 is the dielectric gap-filling layer and is a molding compound and in physical contact with the stress-relief layer [element 108]).
[claim 26] The method of claim 21, wherein the top die comprises a semiconductor substrate and an interconnect structure under the semiconductor substrate, and wherein the stress relief layer has a top end higher than an interface between the semiconductor substrate and the interconnect structure, and the top end is lower than an additional top surface of the top die (figure 7, paragraphs 0042 and 0049, where the top die [element 50] comprises a semiconductor substrate [element 72] and an interconnect structure under the substrate [element 132 and 136 comprise the interconnect layer underneath the substrate [element 72], where the stress relief layer has a top portion lower than the top portion of the die [element 50] but higher than the interconnect structure [elements 132 and 136]).
[claim 27] The method of claim 21, wherein in a top view of the stress relief layer, the second portion forms a ring encircling the first portion (figure 16A, paragraph 0066, where element 108 encircles element 50 from a top down perspective).
[claim 28] A method comprising: bonding a top die over a bottom die, wherein the top die comprises: a semiconductor substrate; and an interconnect structure under the semiconductor substrate (figure 2, paragraph 0017-0018 where the top die, element 50, comprises a substrate [element 52], and an interconnect structure [layer 58 with element 56] underneath the substrate),
forming a stress relief layer comprising a first portion contacting a first sidewall of the interconnect structure, wherein a top end of the stress relief layer is higher than an interface between the semiconductor substrate and the interconnect structure, and wherein the top end of the stress relief layer is lower than a top surface of the semiconductor substrate (figure 3, paragraphs 0018 and 0042, where the stress relief layer [element 108] has a first portion directly contacting the sidewall of the interconnect structure, and a top portion of the stress relief layer high than the interface between element 52 [substrate] and element 58 [interconnect layer – contains element 56 as well], and the top end of element 108 [stress relief] is lower than the top surface of the substrate [element 52]),
and forming a dielectric gap-filling region on the stress relief layer (figure 4, paragraph 0042, where element 110 is the dielectric gap-filling material overlaying the stress relief layer [element 108], where the dielectric gap-filling region is the region that surrounds the entire die [element 50]).
[claim 29] The method of claim 28, wherein the dielectric gap-filling region is further in physical contact with a second sidewall of the semiconductor substrate (figure 4, paragraph 0042, where the dielectric gap-filling region is in contact with both sidewalls fo the semiconductor substrate – note “region” is interpreted broadly to encompass the area under which the dielectric layer is overlayed and a different material can be in said region as well. It is recommended that applicant discloses a layer with material rather than just an abstract “region”).
[claim 30] The method of claim 28, wherein the dielectric gap-filling region is further in physical contact with an additional top surface of the bottom die (figure 4, paragraph 0042, where the dielectric gap-filling region is in contact with top surface of the semiconductor substrate – note “region” is interpreted broadly to encompass the area under which the dielectric layer is overlayed and a different material can be in said region as well. It is recommended that applicant discloses a layer with material rather than just an abstract “region”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al (US 20220068856) in view of Su et al (US 20110031603).
Chiou et al teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 4] The method of claim 1 further comprising: forming a patterned etching mask on the stress relief layer; performing an etching process to remove portions of the stress relief layer; and removing the patterned etching mask.
[claim 5] The method of claim 4, wherein one of the portions of the stress relief layer removed in the etching process is on a top surface of the bottom die.
[claim 6] The method of claim 1, wherein the stress relief layer comprises a metal- containing dielectric material.
However, Su et al does teach
[claim 4] The method of claim 1 further comprising: forming a patterned etching mask on the stress relief layer figure 5, paragraphs 0022-0023, where element 170 is the etching mask and patterned on the stress relief layer [element 178]);
performing an etching process to remove portions of the stress relief layer (figure 6, paragraph 0023, where the etching process removes a portion of element 178, the stress relief layer);
and removing the patterned etching mask (figure 6, paragraph 0026, where element 170 is the etching mask and is removed).
[claim 5] The method of claim 4, wherein one of the portions of the stress relief layer removed in the etching process is on a top surface of the bottom die (figure 5, paragraph 0017, where element 178 is the stress relief layer and a portion is removed that is situated over a top portion of the die [element 104]).
[claim 6] The method of claim 1, wherein the stress relief layer comprises a metal- containing dielectric material (paragraph 0023, where the stress relief layer, element 178, contains metal and is a dielectric layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Su et al to etch the stress-relief layer with an etch mask to allow for precision etching of the layer in a matter to only allow portions of the semiconductor device to be etched while others are not – thus improving precision of the method.
Claim(s) 8-10 and 22, 24, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al (US 20220068856) in view of Hu et al (US 20130009288).
Chiou et al teaches all of the limitations of the parent claim, claims 1 and 21, but does not specifically disclose
[claim 8] The method of claim 1, wherein the dielectric gap-filling layer comprises: a dielectric liner; and a dielectric layer over the dielectric liner.
[claim 9] The method of claim 8, wherein the stress relief layer and the dielectric liner are formed of a same material, and the stress relief layer is formed with a higher deposition rate than the dielectric liner.
[claim 10] The method of claim 8, wherein the stress relief layer and the dielectric liner are formed of a same material, and the stress relief layer has a lower density than the dielectric liner.
[claim 22] The method of claim 21, wherein the stress relief layer further comprises a third portion contacting a top surface of the top die.
[claim 24] The method of claim 21, wherein the dielectric gap-filling region is formed by processes comprising :forming a dielectric liner; and forming a dielectric layer over and contacting the dielectric liner, wherein the dielectric liner comprises a different material than the dielectric layer.
[claim 25] The method of claim 24, wherein the dielectric liner and the stress relief layer comprise a same material, and the stress relief layer has a lower density than the dielectric liner.
However, Hu et al teaches
[claim 8] The method of claim 1, wherein the dielectric gap-filling layer comprises: a dielectric liner; and a dielectric layer over the dielectric liner (figure 4, paragraph 0024, where element 18 is the stress relief layer, and element 26 is the dielectric layer made of a dielectric liner [element 28] and a dielectric layer [element 30]).
[claim 9] The method of claim 8, wherein the stress relief layer and the dielectric liner are formed of a same material, and the stress relief layer is formed with a higher deposition rate than the dielectric liner (figure 4, paragraphs 0018 and 0024, where elements 18 and 26 are made of the same material but the stress layer has a higher deposition rate than the dielectric liner [element 28]).
[claim 10] The method of claim 8, wherein the stress relief layer and the dielectric liner are formed of a same material, and the stress relief layer has a lower density than the dielectric liner (figure 4, paragraphs 0018 and 0024, where elements 18 and 26 are made of the same material but the stress layer has a lower density than the dielectric liner [element 28]).
[claim 22] The method of claim 21, wherein the stress relief layer further comprises a third portion contacting a top surface of the top die (figure 4, paragraph 0024, element 18 is in place of the stress relief layer 108 of Chiou et al, and further comprises a third portion that covers the top of the die [element 14 in place of the die of Chiou et al]).
[claim 24] The method of claim 21, wherein the dielectric gap-filling region is formed by processes comprising :forming a dielectric liner; and forming a dielectric layer over and contacting the dielectric liner, wherein the dielectric liner comprises a different material than the dielectric layer (figure 4, paragraph 0024, where element 26 is the dielectric layer in place of element 110 of Chiou et al [dielectric layer] and comprises a dielectric liner [element 28] made of a different material than the dielectric layer [element 30]).
[claim 25] The method of claim 24, wherein the dielectric liner and the stress relief layer comprise a same material, and the stress relief layer has a lower density than the dielectric liner (figure 4, paragraph 0024, element 18 is in place of the stress relief layer 108 of Chiou et al, and futher comprises a third portion that covers the top of the die [element 14 in place of the die of Chiou et al]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Chiou et al to incorporate the teachings of Hu et al in order to allow for a dielectric liner with the dielectric layer to maximize the effects of the dielectric layer – namely electrical insulation and structural integrity of the semiconductor package.
Allowable Subject Matter
Claims 2-3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang et al (US 20230010707), Kim et al (US 20230005842), Kao et al (US 20220301970), Chen et al (US 11404342), and Chen et al (US 20200006309) as packages and methods of creating packages with semiconductor devices and stress relief layers included with dielectric layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANDREW JOHN ZABEL/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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