Prosecution Insights
Last updated: August 16, 2026
Application No. 18/610,394

GATE TRENCH POWER SEMICONDUCTOR DEVICES HAVING TRENCH SHIELDING REGIONS AND METHODS OF FORMING THE SAME

Non-Final OA §102
Filed
Mar 20, 2024
Examiner
SPALLA, DAVID C
Art Unit
Tech Center
Assignee
Wolfspeed Inc.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
720 granted / 853 resolved
+24.4% vs TC avg
Minimal +5% lift
Without
With
+4.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
17 currently pending
Career history
865
Total Applications
across all art units

Statute-Specific Performance

§103
52.3%
+12.3% vs TC avg
§102
31.3%
-8.7% vs TC avg
§112
9.5%
-30.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 853 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 08/27/2024 and 07/02/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-7 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2021/0408279 to Siemieniec et al (hereinafter Siemieniec). Regarding Claim 1, Siemieniec discloses a semiconductor device, comprising: a semiconductor layer structure that comprises a drift region having a first conductivity type (Fig. 1G, 131) and a trench shielding region (162) having a second conductivity type; and a gate trench (155) extending in a longitudinal direction in the semiconductor layer structure, wherein the trench shielding region extends in the longitudinal direction underneath the gate trench (Fig. 1G), and at least a portion of the trench shielding region comprises sidewalls that angle inwardly with increasing distance from the gate trench (Fig. 1G). Regarding Claim 2, Siemieniec discloses the semiconductor device of Claim 1, wherein the portion of the trench shielding region comprises at least a lower half of the trench shielding region (Fig. 1G). Regarding Claim 3, Siemieniec discloses the semiconductor device of Claim 2, wherein the sidewalls of the portion of the trench shielding region angle inwardly with increasing distance from the gate trench in a direction perpendicular to a lower surface of the semiconductor layer structure (Fig. 1G). Regarding Claim 4, Siemieniec discloses the semiconductor device of Claim 2, wherein a maximum width of the portion of the trench shielding region is less than or equal to a maximum width of the gate trench (Fig. 1G). Regarding Claim 5, Siemieniec discloses the semiconductor device of Claim 2, wherein the semiconductor layer structure further comprises first and second support shields having the second conductivity type and extending in the longitudinal direction on first and second sides of the gate trench, respectively (Fig. 1G). Regarding Claim 6, Siemieniec discloses the semiconductor device of Claim 5, wherein a portion of the drift region is between the first support shield and the trench shielding region and has a width that is substantially constant or increases with increasing depth in the semiconductor layer structure (Fig. 1G). Regarding Claim 7, Siemieniec discloses the semiconductor device of Claim 6, wherein the width of the portion of the drift region increases with increasing depth in the semiconductor layer structure (Fig. 1G). Regarding Claim 10, Siemieniec discloses the semiconductor device of Claim 2, wherein an upper portion of the trench shielding region is between the gate trench and a lower portion of the trench shielding region and has a higher second conductivity type doping concentration than the lower portion of the trench shielding region (Fig. 1G, overlapping 161 and 162 doped regions). Regarding Claim 11, Siemieniec discloses the semiconductor device of Claim 2, further comprising a gate oxide layer and a gate electrode in the gate trench, wherein the semiconductor layer structure further comprises a well region having the second conductivity type on the drift region and a source region having the first conductivity type on the well region (Fig. 1G). Regarding Claim 12, Siemieniec discloses the semiconductor device of Claim 2, wherein the drift region comprises silicon carbide [0033]. Claims 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2020/0381253 to Schulze et al (hereinafter Schulze). Regarding Claim 13, Schulze discloses a semiconductor device, comprising: a semiconductor layer structure that comprises a drift region having a first conductivity type (Fig. 9B, (138, 135) and a trench shielding region (281) having a second conductivity type; and a gate trench (150) extending in a longitudinal direction in the semiconductor layer structure, wherein the trench shielding region extends underneath the gate trench in the longitudinal direction (Fig. 9B), the trench shielding region comprising endwalls that oppose each other along the longitudinal direction and are oblique with respect to a lower surface of the semiconductor layer structure (Fig. 9B). Regarding Claim 14, Schulze discloses the semiconductor device of Claim 13, wherein the endwalls of the trench shielding region extend substantially parallel to each other (Fig. 9B). Regarding Claim 15, Schulze discloses the semiconductor device of Claim 13, wherein the endwalls of the trench shielding region are adjacent an inactive region of the semiconductor device (Fig. 9B). Allowable Subject Matter Claims 18-22 are allowed. Claims 8, 9, 16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 18 recites a semiconductor device, comprising: a semiconductor layer structure that comprises a drift region having a first conductivity type and a trench shielding region having a second conductivity type; and a gate trench extending in a longitudinal direction in the semiconductor layer structure, wherein the trench shielding region extends underneath the gate trench in the longitudinal direction, the trench shielding region comprising an endwall that extends past an endwall of the gate trench in the longitudinal direction. While Siemieniec and Schulze disclose a trench shielding region having extending sidewalls, the sidewalls do not extend past the endwalls of the trench gate. US PG Pub 2025/0169129 (“Zhang”) and US PG Pub 2024/0297250 (“Hung”) are cited as being examples of other, relevant references in the art for comparison to Applicant’s invention. While the references disclose trench shielding regions with extending sidewalls, they similarly do not disclose endwalls that extend past the trench gate sidewalls. Claims 19-22 depend on Claim 18 and are allowable for at least the reasons above. Claims 16 and 17 recite similar subject matter to Claim 18 and are allowable for at least the reasons above. Claims 8 and 9 require structural limitations for the first and second support shields not found in the references of record, in combination with the requirements on the trench shielding region. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID C SPALLA/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Mar 20, 2024
Application Filed
Jul 28, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12701711
MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
2y 2m to grant Granted Aug 04, 2026
Patent 12696746
Backside BPR/BSPDN Intergration with Backside Local Interconnect.
3y 9m to grant Granted Jul 28, 2026
Patent 12696450
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
2y 7m to grant Granted Jul 28, 2026
Patent 12690444
INLINE CIRCUIT EDIT FOR BACKSIDE POWER DELIVERY
4y 2m to grant Granted Jul 21, 2026
Patent 12677600
Tunable Josephson Junction with Added Dopants
2y 7m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
89%
With Interview (+4.8%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 853 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month