Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 2nd, 2025, was filed prior to the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 11-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Anderson et al. (2012/0181588 A1; hereinafter Anderson).
Regarding Claim 1, Anderson (fig. 6) teaches a semiconductor device ([0031], 64), comprising:
a substrate ([0014], 10);
a gate dielectric layer ([0019], 20) over the substrate (10);
a dipole layer ([0017], 16) over the gate dielectric layer (20), wherein the dipole layer (16) is an oxygen-containing layer ([0016]), and
a width of the dipole layer (16) is less than a width (see fig. 6) of the gate dielectric layer (20);
a gate ([0021], 40) over the dipole layer (16) and the gate dielectric layer (20);
a source region ([0034], 52) in the substrate (10); and
a drain region ([0037], 54) in the substrate (10), wherein the source region (52) and the drain region (54) are at opposite sides of the gate dielectric layer (20).
Regarding Claim 2, Anderson (fig. 6) teaches the semiconductor device of claim 1, wherein a sidewall of the dipole layer (16) near the source region (52) is aligned with a sidewall of the gate dielectric layer (20) near the source region (52).
Regarding Claim 3, Anderson (fig. 6) teaches the semiconductor device of claim 1, wherein a sidewall of the dipole layer (16) near the drain region (54) is shifted laterally from a sidewall of the gate dielectric layer (20) near the drain region (54).
Regarding Claim 11, Anderson (fig. 6) teaches a manufacturing method of a semiconductor device ([0031], 64), comprising:
forming a gate dielectric layer ([0019], 20) over a substrate ([0014], 10);
forming a dipole layer ([0017], 16) over the gate dielectric layer (20), wherein the dipole layer (16) covers a portion of the gate dielectric layer (20);
forming a gate ([0021], 40) over the dipole layer (16) and the gate dielectric layer (20); and
forming a source region ([0034], 52) and a drain region ([0037], 54) in the substrate (10), wherein the source region (52) and the drain region (54) are at opposite sides of the gate dielectric layer (20).
Regarding Claim 12, Anderson (fig. 6) teaches the manufacturing method of claim 11, wherein after forming the source region (52) and the drain region (54), a sidewall of the dipole layer (16) near the source region (52) is aligned with a sidewall of the gate dielectric layer (20) near the source region (52).
Regarding Claim 13, Anderson (fig. 6) teaches the manufacturing method of claim 11, wherein after forming the source region (52) and the drain region (54), a sidewall of the dipole layer (16) near the drain region (54) is shifted laterally from a sidewall of the gate dielectric layer (20) near the drain region (54).
Regarding Claim 14, Anderson (fig. 6) teaches the manufacturing method of claim 11, wherein after forming the source region (52) and the drain region (54), the gate (40) near the drain region (54) is in contact with the gate dielectric layer (20) near the drain region (54).
Regarding Claim 15, Anderson (fig. 6) teaches the manufacturing method of claim 11, wherein a thickness of the gate (40) near the source region (52) is less than a thickness of the gate (40) near the drain region (54).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 4-8 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson as applied to Claims 1 and 11 above, and further in view of Chidambarrao (2011/0163385 A1; hereinafter Chidambarrao).
Regarding Claim 4, Anderson doesn’t teach the semiconductor device of claim 1, further comprising: a high-k gate dielectric layer between the gate dielectric layer and the dipole layer, wherein a dielectric constant of the high-k gate dielectric layer is higher than a dielectric constant of the gate dielectric layer.
However, Chidambarrao (fig. 4) teaches a high-k gate dielectric layer ([0021], 16) between the gate dielectric layer ([0028], chemox layer not shown) and the dipole layer ([0038], 26), wherein a dielectric constant of the high-k gate dielectric layer (16) is higher than a dielectric constant ([0028]-[0029]) of the gate dielectric layer (chemox). Chidambarrao also teaches that a high-k dielectric has a greater dielectric constant ([0029]) and therefore acts as a better insulator.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Anderson to include the high-k gate dielectric layer of Chidambarrao to improve insulation.
Regarding Claim 5, the combination of Anderson and Chidambarrao teaches the semiconductor device of claim 4, wherein the high-k gate dielectric layer (Chidambarrao, 16) is in contact with the gate (Anderson, 40).
Regarding Claim 6, Chidambarrao (fig. 4) teaches the semiconductor device of claim 4, wherein the width of the dipole layer (26) is less than a width (the sloped portion of 26 has a smaller width than 16, see fig. 4) of the high-k gate dielectric layer (16).
Regarding Claim 7, the combination of Anderson and Chidambarrao teaches the semiconductor device of claim 4, wherein a sidewall of the dipole layer (Anderson, 16) near the source region (Anderson, 52) is aligned with a sidewall of the high-k gate dielectric layer (Chidambarrao, 16) near the source region (Anderson, 52).
Regarding Claim 8, the combination of Anderson and Chidambarrao teaches the semiconductor device of claim 4, wherein a sidewall of the dipole layer (Anderson, 16) near the drain region (Anderson, 54) is shifted laterally from a sidewall of the high-k gate dielectric layer (Chidambarrao, 16) near the drain region (Anderson, 54).
Regarding Claim 16, Anderson doesn’t teach the manufacturing method of claim 11, further comprising: forming a high-k gate dielectric layer over the gate dielectric layer before forming the dipole layer, wherein after forming the dipole layer, the dipole layer exposes a portion of the high-k gate dielectric layer.
However, Chidambarrao (fig. 4) teaches forming a high-k gate dielectric layer ([0021], 16) over the gate dielectric layer ([0028], chemox layer not shown) before forming the dipole layer ([0038], 26), wherein after forming the dipole layer, the dipole layer exposes a portion of the high-k gate dielectric layer. Chidambarrao also teaches that a high-k dielectric has a greater dielectric constant ([0029]) and therefore acts as a better insulator.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Anderson to include the high-k gate dielectric layer of Chidambarrao to improve insulation. The combination of Anderson and Chidambarrao further teaches after forming the dipole layer (Anderson, 16), the dipole layer (Anderson, 16) exposes a portion of the high-k gate dielectric layer (Chidambarrao, 16).
Regarding Claim 17, the combination of Anderson and Chidambarrao teaches the manufacturing method of claim 16, wherein after forming the source region (Anderson, 52) and the drain region (Anderson, 54), the gate (Anderson, 40) near the drain region (Anderson, 54) is in contact with the high-k gate dielectric layer (Chidambarrao, 16) near the drain region (Anderson, 54).
Regarding Claim 18, the combination of Anderson and Chidambarrao teaches the manufacturing method of claim 16, wherein after forming the source region (Anderson, 52) and the drain region (Anderson, 54), a sidewall of the dipole layer (Anderson, 16) near the source region (Anderson, 52) is aligned with a sidewall of the high-k gate dielectric layer (Chidambarrao, 16) near the source region (Anderson, 52).
Claims 9-10 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Anderson as applied to Claims 1 and 11 above, and further in view of Lee (2020/0194267 A1; hereinafter Lee).
Regarding Claim 9, Anderson doesn’t teach the semiconductor device of claim 1, wherein a sidewall of the dipole layer near the drain region is aligned with a sidewall of the gate dielectric layer near the drain region.
However, Lee (annotated fig. 1B) teaches a sidewall of the dipole layer ([0048], upper portion of 102, referred to as dipole layer, see annotated fig. 1B) near the drain region ([0037], 105) is aligned with a sidewall of the gate dielectric layer (lower portion of 102, referred to as gate dielectric layer, see annotated fig. 1B) near the drain region (105). Lee also teaches that this reduces electric field between the gate and drain and therefore reduces the hot carrier effect.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Anderson to include the asymmetry of Lee to reduce the hot carrier effect.
PNG
media_image1.png
587
797
media_image1.png
Greyscale
Annotated Figure 1B
Regarding Claim 10, Anderson doesn’t teach the semiconductor device of claim 1, wherein a sidewall of the dipole layer near the source region is shifted laterally from a sidewall of the gate dielectric layer near the source region.
However, Lee (annotated fig. 1B) teaches a sidewall of the dipole layer ([0048], upper portion of 102, referred to as dipole layer, see annotated fig. 1B) near the source region ([0037], 104) is shifted laterally from a sidewall of the gate dielectric layer (lower portion of 102, referred to as gate dielectric layer, see annotated fig. 1B) near the source region (104). Lee also teaches that this reduces electric field between the gate and drain and therefore reduces the hot carrier effect.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Anderson to include the asymmetry of Lee to reduce the hot carrier effect.
Regarding Claim 19, Anderson doesn’t teach the manufacturing method of claim 11, wherein after forming the source region and the drain region, a sidewall of the dipole layer near the drain region is aligned with a sidewall of the gate dielectric layer near the drain region.
However, Lee (annotated fig. 1B) teaches after forming the source region ([0037], 104) and the drain region ([0037], 105), a sidewall of the dipole layer ([0048], upper portion of 102, referred to as dipole layer, see annotated fig. 1B) near the drain region (105) is aligned with a sidewall of the gate dielectric layer (lower portion of 102, referred to as gate dielectric layer, see annotated fig. 1B) near the drain region (105). Lee also teaches that this reduces electric field between the gate and drain and therefore reduces the hot carrier effect.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Anderson to include the asymmetry of Lee to reduce the hot carrier effect.
Regarding Claim 20, Anderson doesn’t teach the manufacturing method of claim 11, wherein after forming the source region and the drain region, a sidewall of the dipole layer near the source region is shifted laterally from a sidewall of the gate dielectric layer near the source region.
However, Lee (annotated fig. 1B) teaches after forming the source region ([0037], 104) and the drain region ([0037], 105), a sidewall of the dipole layer ([0048], upper portion of 102, referred to as dipole layer, see annotated fig. 1B) near the source region (104) is shifted laterally from a sidewall of the gate dielectric layer (lower portion of 102, referred to as gate dielectric layer, see annotated fig. 1B) near the source region (104). Lee also teaches that this reduces electric field between the gate and drain and therefore reduces the hot carrier effect.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Anderson to include the asymmetry of Lee to reduce the hot carrier effect.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADIN HRNJIC whose telephone number is (571)270-1794. The examiner can normally be reached Monday-Friday 8:00 AM - 4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights