DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15-23 and 25-33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (2022/0320299).
Re claim 15, Chen discloses (Fig. 7) forming a device layer comprising a plurality of semiconductor devices (10) in and over a substrate (900); forming a first interconnect structure (150B) over a first side of the device layer (Fig. 5), wherein the first interconnect structure comprises a plurality of intermetal dielectric (IMD) layers ([0020]), and a first stack of conductors (240A/240B) through the first interconnect structures and embedded in the plurality of IMD layers; forming a backside conductor (500) in the device layer from a second side of the device layer, wherein the backside conductor (500) is electrical connection with the first stack of conductors; and forming a second interconnect structure (250A) over the second side of the device layer (Fig. 5), wherein the second interconnect structure includes an electrically conductive path to the backside conductor (500).
Re claim 16, Chen discloses further comprising: forming a front side conductor (150A) in the device layer from the first side of the device layer, wherein the first stack of conductors (240A/240B) is in contact with the front side conductor (Fig. 6).
Re claim 17, Chen discloses wherein the backside conductor (240A/240B) is formed over and in contact with the front side conductor (140A/140B).
Re claim 18, Chen discloses further comprising: forming a middle conductor (140A/140B) in the device layer prior to forming the front side conductor (150A), wherein the middle conductor is a conductive line along a first direction, the front side conductor and the backside conductor are conductive lines along a second direction, and the middle conductor is in contact with the front side conductor and the backside conductor (Fig. 6).
Re claim 19, Chen discloses wherein forming the middle conductor (140A/140B) is performed simultaneously with forming source/drain contacts (125) to the plurality of semiconductor devices and forming the front side conductor is performed simultaneously with forming gate contacts to the plurality of semiconductor devices (Fig. 1~ [0031]).
Re claim 20, Chen discloses wherein the second interconnect structure (250A) includes a backside power delivering network (PDN) (140B/150B~ [0048]).
Re claim 21, Chen discloses (Fig. 7) providing a first integrated circuit chip comprising: a device layer having a plurality of semiconductor devices (10); a first interconnect structure (150B) disposed over a first side of the device layer (Fig. 5); a second interconnect structure (250A) disposed over a second side of the device layer; and a via tower (140A/140B/150B/250A/240A/240B) configured to provide an electrical connection through the first interconnect structure, the device layer, and the second interconnect structure, wherein the via tower comprises a stack of conductors formed through the device layer and at least one of the first and second interconnect structures (Fig. 6); and bonding a second integrated circuit chip to the first integrated circuit chip, wherein the via tower is in electrical connection with the second integrated circuit chip via a bond pad feature ([0060]).
Re claim 22, Chen discloses wherein the via tower comprises: a first stack of conductors (240A/240B) disposed through the first interconnect structure; and a second stack of conductors (140A/140B) disposed through the device layer, wherein the second stack of conductors is in contact with the first stack of conductors, and the bond pad feature is in contact with the first stack of conductors (Fig. 5).
Re claim 23, Chen discloses Chen discloses wherein the second interconnect structure (250A) includes a backside power delivering network (PDN) (140B/150B~ [0048]).
Re claim 25, Chen discloses wherein the second stack of conductors comprises: a front side conductor (140A) disposed in the first side of the device layer; and a backside conductor (140B) disposed in the second side of the device layer.
Re claim 26, Chen discloses wherein the second stack of conductors comprises: a middle conductor (140A/140B) disposed between the front side conductor (140A) and the backside conductor (140B), wherein the front side conductor and the backside conductor are conductive lines along a first direction and the middle conductor is a conductive line along a second direction (Fig. 6).
Re claim 27, Chen discloses forming a device layer on a front side of a substrate (10), wherein the device layer comprises a plurality of semiconductor device and a device layer conductor stack in the device layer; forming a first interconnect structure (150B) over the device layer, wherein the first interconnect structure includes a front side conductor stack (140A/140B) in electrical connection with the device layer conductor stack; flipping over the substrate; and forming a second interconnect structure (250A) on a back side of the device layer, wherein the second interconnect structure includes a back side conductor stack (500) in electrical connection with the device layer conductor stack, and the front side conductor stack, the device layer conductor stack, and the back side conductor stack form a via tower (Fig. 7).
Re claim 28, Chen discloses wherein the first interconnect structure comprises a plurality of intermetal dielectric (IMD) layers ([ILD]), and the front side conductor stack comprises a plurality of embedded conductors in the plurality of IMD layer ([0020]).
Re claim 29, Chen discloses wherein each of the embedded conductors comprises: a conductive plate; and a via bar in contact with the conductive plate ([0044]~ Fig. 1).
Re claim 30, Chen discloses wherein each of the embedded conductors comprises: a conductive plate; and an array of vias in contact with the conductive plate ([0044]).
Re claim 31, Chen discloses Chen discloses wherein the second interconnect structure (250A) includes a backside power delivering network (PDN) (140B/150B~ [0048]).
Re claim 32, Chen discloses wherein the device layer conductor stack comprises: a front side conductor (140A) disposed in the first side of the device layer; and a backside conductor (140B) disposed in the second side of the device layer.
Re claim 33, Chen discloses wherein the second stack of conductors comprises: a middle conductor (140A/140B) disposed between the front side conductor (140A) and the backside conductor (140B), wherein the front side conductor and the backside conductor are conductive lines along a first direction and the middle conductor is a conductive line along a second direction (Fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 24 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claims 15-23 and 15-22 above, and further in view of the following comments.
Re claim 24, Chen does not clearly disclose wherein the via tower further comprises: a third stack of conductors disposed through the second interconnect structure, wherein the third stack of conductors is in contact with the second stack of conductors.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to add a third stack of conductors disposed through the second interconnect structure, wherein the third stack of conductors is in contact with the second stack of conductors, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Re claim 34, , it would have been an obvious matter of design choice bounded by well known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions (plurality and shape) because applicant has not disclosed that the dimensions (plurality and shape) are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension (plurality and shape). Indeed, it has been held that mere dimensional limitations (plurality and shape) are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2024/0088078 A1, US 2022/0367210 A1, US 2021/0366863 A1, US 2021/0159212 A1, US 2024/0203941 A1, US 2024/0332183 A1 and US 2025/0219002 A1 disclose a similar method for forming an integrated circuit chip with interconnect structures and backside conductor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHELLE MANDALA whose telephone number is (571)272-1858. The examiner can normally be reached 8:00-5:00 PM.
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/MICHELLE MANDALA/Primary Examiner, Art Unit 2893 August 25, 2026
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