DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 6 July 2026 is acknowledged. Applicant cancelled claims 11-20 drawn to Invention II. Claims 1-10 are examined. The Restriction/Election Requirement is made final.
Claim Objections
Claim 5 is objected to because of the following informalities:
the preamble reads “[t]he semiconductor device of claim 1, further comprises a…” which is grammatically incorrect.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu (US 2019/0259839) and Yoo et al. (“Yoo” US 2019/0393320).
Regarding claim 1, Ryu teaches a semiconductor device (Figure 15), comprising:
a substrate (101);
an active region (104) in the substrate (101); and
a gate structure (106-108) in the active region (104), the gate structure comprising a bottom lining layer (106, portion adjacent to the conductive layers 107 and 108), and a bottom conductive material layer (107 and 108, formed in the bottom lining layer 106).
Ryu does not teach a bottom low work function material layer formed in the bottom lining layer, where the bottom conductive material layer is formed in the bottom low work function material layer.
Yoo teaches a bottom low work function material layer (31, Figure 1D, para. [0068]) formed in the bottom lining layer (20), where the bottom conductive material layer (50) is formed in the bottom low work function material layer (31, see Figure 1D).
It would have been obvious to incorporate the teachings of Yoo into the teachings of Ryu to include the bottom low work function material layer in the lining layer and the conductive layer formed in the low work function material layer as claimed for the purpose of mitigating gate induced drain leakage (Yoo, para. [0072]).
Regarding claim 2, Ryu teaches wherein a material of the bottom conductive material layer (107/108) comprises titanium nitride (para. [0068], [0070]).
Regarding claim 3, Yoo teaches wherein a material of the bottom low work function material layer (31) comprises a polycrystalline silicon or an amorphous silicon (polysilicon, para. [0068]).
Regarding claim 4, Ryu teaches wherein a material of the bottom lining layer (106, portion adjacent to the conductive material layer 107/108) comprises silicon oxide (para. [0066]).
Regarding claim 5, Ryu further teaches a residual lining layer (106, portion above the conductive material layer 107/108) above the bottom lining layer (106, portion adjacent to the conductive material layer 107/108) and located higher than the bottom low work function material layer (as incorporated by Yoo, between 107/108 and 106 of Ryu) and the bottom conductive material layer (107/108, see Figure 15).
Regarding claim 6, Ryu teaches wherein a thickness of the residual lining layer (106, portion above the conductive material layer 107/108) is thinner than a thickness of the bottom lining layer (106, portion adjacent to the conductive material layer 107/108, see D1 and D2 of Figure 15).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu and Yoo as applied to claim 6 above, and further in view of Huh et al. (“Huh” US 2013/0256770).
Regarding claim 7, Ryu does not explicitly teach a barrier layer formed in the residual lining layer.
Huh teaches a barrier layer (239) formed in the residual lining layer (24, see Figure 7).
It would have been obvious to incorporate the teachings of Huh into the teachings of Ryu and Yoo to include the barrier layer as claimed for the purpose of reducing a leakage current between the gate electrode and the source/drain (Huh, para. [0175]).
Regarding claim 8, the combination of Ryu/Yoo and Huh teaches a dielectric layer (111 of Ryu, 245 of Huh) formed in the barrier layer (incorporated by Huh, 239, in which the dielectric layer 245 is formed, analogous to dielectric layer 111 of Ryu, thus incorporating the barrier layer 239 of Huh also teaches the limitation of claim 8).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu and Yoo as applied to claim 1 above, and further in view of Lee et al. (“Lee” US 2024/0206159).
Regarding claim 9, Ryu teaches an isolation region (102) in the substrate (101).
Ryu does not teach a dummy gate structure in the isolation region, wherein the dummy gate structure extends deeper than the gate structure in the substrate.
Lee teaches (Figures 11A-16B) an isolation region (region of 104) in the substrate (102); and
a dummy gate structure in the isolation region (see gate structure 122 in isolation region of 104), wherein the dummy gate structure extends deeper than the gate structure (gate structure outside of isolation region of 104) in the substrate (102, see LV1/LV2 in Figure 11B)
It would have been obvious to incorporate the teachings of Lee into the teachings of Ryu/Yoo to include the isolation structure and dummy gate structure as claimed because a dummy gate structure provides structural support, and the different depths of the gate structures are a result of different etch rates of the active region and isolation region materials (Lee, para. [0122]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu, Yoo, and Lee as applied to claim 9 above, and further in view of Kim et al. (“Kim” US 2010/0117148).
Regarding claim 10, Ryu teaches wherein the isolation region (102) comprises an oxide layer (para. [0058]) directly in contact with the active region (104).
Ryu and Lee do not teach a nitride layer sandwiched by the oxide layer.
Kim teaches an isolation region (58, Figure 4A) comprising an oxide layer (55 and 57, para. [0036]) and a nitride layer (56, para. [0036]) sandwiched by the oxide layer (see Figure 4A).
It would have been obvious to incorporate the teachings of Kim into the teachings of Ryu/Yoo/Lee to include the oxide and nitride layers of the isolation structure as claimed. The combination would result in the predictable result to a person having ordinary skill in the art of using a nitride to block diffusion of the oxide layer. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights