Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 09, 2025 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 46 is objected to because of the following informalities: Claim 46 depends on claim 44. It seems that claim 46 should depend on claim 45 in order to avoid a lack of antecedent basis for the term “the conductive via” . Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 14, 44 and 47-50 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gatterbauer et al. (Pub. No.: US 2020/0111754 A1).
Regarding Claim 1, Gatterbauer et al. discloses a semiconductor device, comprising: a semiconductor die (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – semiconductor die comprising substrate 104 or substrate together with interlevel dielectric 104); and
PNG
media_image1.png
622
564
media_image1.png
Greyscale
a metal contact structure on the semiconductor die, the metal contact structure comprising a first metal layer structure (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – metal contact structure comprising a first metal layer structure comprising layers 100 (structured interlayer) and 108 (structured metallization)); wherein the first metal layer structure comprises an intermediate layer and a first metal contact layer on the intermediate layer (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – first metal layer structure comprising intermediate layer 100 (structured interlayer) and first metal contact layer 108 (structured metallization)); wherein an outer edge of the first metal contact layer is inset from an outer edge of the intermediate layer so that a peripheral portion of the intermediate layer extends farther outward than the outer edge of the first metal contact layer (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D). .
Regarding Claim 2, Gatterbauer et al., as applied to claim 1, discloses
the semiconductor device, further comprising a protective layer on the peripheral portion of the first metal contact layer and the outer edge of the intermediate layer (Par. 0046-0050; Fig. 9D – protective layer 908 (barrier)).
Regarding Claim 3, Gatterbauer et al., as applied to claim 2, discloses
the semiconductor device, wherein the protective layer comprises a passivation layer on the peripheral portion of the first metal contact layer and the outer edge of the intermediate layer (Par. 0046-0050; Fig. 9D – protective layer 908 (barrier) formed of SiN, SiO, SiCN etc. also acts as a passivation layer).
Regarding Claim 4, Gatterbauer et al., as applied to claim 3, discloses
the semiconductor device, further comprising a polyimide layer on the passivation layer (Par. 0050; Fig. 9D – polyimide layer 910).
Regarding Claim 5, Gatterbauer et al., as applied to claim 2, discloses
the semiconductor device, wherein the protective layer comprises a polyimide layer on the peripheral portion of the first metal contact layer and the outer edge of the intermediate layer (Par. 0050; Fig. 9D – polyimide layer 910).
Regarding Claim 14, Gatterbauer et al., as applied to claim 1, discloses
the semiconductor device, wherein the first metal contact layer comprises copper, and wherein the intermediate layer comprises titanium nitride, titanium tungsten and/or tantalum nitride (Par. 0024).
Regarding Claim 44, Gatterbauer et al. discloses a semiconductor device, comprising: a semiconductor die (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – semiconductor die comprising substrate 104 or substrate together with interlevel dielectric 104); a metal layer structure on the semiconductor die (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – metal layer structure comprising layers 100 (structured interlayer) and 108 (structured metallization)); wherein the metal layer structure comprises an intermediate layer on the semiconductor die and a metal contact layer on the intermediate layer (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – metal layer structure comprising intermediate layer 100 (structured interlayer) and metal contact layer 108 (structured metallization));
PNG
media_image1.png
622
564
media_image1.png
Greyscale
wherein an outer edge of the metal contact layer is inset from an outer edge of the intermediate layer so that a peripheral portion of the intermediate layer extends farther outward than the outer edge of the metal contact layer (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D).
Regarding Claim 47, Gatterbauer et al., as applied to claim 44, discloses
the semiconductor device, further comprising a protective layer on the peripheral portion of the metal contact layer and the outer edge of the intermediate layer (Par. 0046-0050; Fig. 9D – protective layer 908 (barrier)).
Regarding Claim 48, Gatterbauer et al., as applied to claim 47, discloses
the semiconductor device, wherein the protective layer comprises a passivation layer on the peripheral portion of the metal contact layer and the outer edge of the intermediate layer (Par. 0046-0050; Fig. 9D – protective layer 908 (barrier) formed of SiN, SiO, SiCN etc. also acts as a passivation layer).
Regarding Claim 49, Gatterbauer et al., as applied to claim 48, discloses
the semiconductor device, further comprising a polyimide layer on the passivation layer (Par. 0050; Fig. 9D – polyimide layer 910).
Regarding Claim 50, Gatterbauer et al., as applied to claim 47, discloses
the semiconductor device, wherein the protective layer comprises a polyimide layer on the peripheral portion of the metal contact layer and the outer edge of the intermediate layer (Par. 0050; Fig. 9D – polyimide layer 910).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6-9 and 15 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Gatterbauer et al. (Pub. No.: US 2020/0111754 A1), as applied to claim 1, or, in the alternative, under 35 U.S.C. 103 as obvious over Gatterbauer et al. (Pub. No.: US 2020/0111754 A1), as applied to claim 1.
Regarding Claim 6, Gatterbauer et al., as applied to claim 1, at least implicitly discloses
the semiconductor device, wherein the intermediate layer comprises a first intermediate layer, the metal contact structure further comprising a second metal layer structure on the first metal layer structure, the second metal layer structure comprising a second intermediate layer on the first metal contact layer and a second metal contact layer on the second intermediate layer (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – first intermediate layer 100 (structured interlayer); although this prior art does not explicitly disclose the metal contact structure further comprising a second metal layer structure on the first metal layer structure, the second metal layer structure comprising a second intermediate layer on the first metal contact layer and a second metal contact layer on the second intermediate layer, its presence is implied; in IC industry, a device is generally formed of quite a few levels of metallization layers; this prior art shows one of the levels and does not explicitly mention presence of other levels; however, it is understood that there are others levels above in order to make contact with external circuitries).
In the alternative, assuming arguendo that Gatterbauer et al. is not emphatic enough regarding the semiconductor device, wherein the metal contact structure further comprising a second metal layer structure on the first metal layer structure, the second metal layer structure comprising a second intermediate layer on the first metal contact layer and a second metal contact layer on the second intermediate layer, The Examiner takes OFFICIAL NOTICE that in a typical IC backend of line (BEOL) metal stack, the metal contact structures adapted in different levels of a device have many similarities to each other. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the semiconductor device, wherein the metal contact structure further comprising a second metal layer structure on the first metal layer structure of Gatterbauer et al., the second metal layer structure comprising a second intermediate layer on the first metal contact layer and a second metal contact layer on the second intermediate layer in order to make contact with external circuitries.
Regarding Claim 7, modified Gatterbauer et al., as applied to claim 6, discloses
the semiconductor device, wherein the first intermediate layer and the second intermediate layer comprise titanium nitride, titanium tungsten and/or tantalum nitride (Gatterbauer et al. - Par. 0024, 0048 in light of rejection of claim 6).
Regarding Claim 8, modified Gatterbauer et al., as applied to claim 7, discloses
the semiconductor device, wherein the first intermediate layer comprises titanium nitride and the second intermediate layer comprises titanium tungsten (Gatterbauer et al. - Par. 0024, 0048 in light of rejection of claim 7; the primary reference teaches that the first intermediate layer comprises titanium nitride and/or titanium tungsten; modified Gatterbauer et al. teaches the first intermediate layer and the second intermediate layer comprise titanium nitride, and/or titanium tungsten; which particular materials are chosen for the different intermediate layers would depend on the type and amount of stress that would get generated due to the deposition of the first and second contact layers).
Regarding Claim 9, modified Gatterbauer et al., as applied to claim 7, discloses
the semiconductor device, wherein the first metal contact layer and the second metal contact layer comprise copper, and wherein the first intermediate layer and the second intermediate layer comprise titanium tungsten (Gatterbauer et al. - Par. 0024 in light of rejection of claim 7).
Regarding Claim 15, Gatterbauer et al., as applied to claim 14, at least implicitly discloses
the semiconductor device, further comprising a second metal contact layer comprising copper on the first metal contact layer (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – first metal contact layer 108; although this prior art does not explicitly disclose a second metal contact layer comprising copper on the first metal contact layer, its presence is implied; in IC industry, a device is generally formed of quite a few levels of metallization layers; this prior art shows one of the levels and does not explicitly mention presence of other levels; however, it is understood that there are others levels above in order to make contact with external circuitries and these levels have much similarities with each other in terms of materials used in each level).
In the alternative, assuming arguendo that Gatterbauer et al. is not emphatic enough regarding the semiconductor device, further comprising a second metal contact layer comprising copper on the first metal contact layer, The Examiner takes OFFICIAL NOTICE that in a typical IC backend of line (BEOL) metal stack, the metal contact structures adapted in different levels of a device have many similarities to each other. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the semiconductor device, further comprising a second metal contact layer comprising copper on the first metal contact layer of Gatterbauer et al., in order to make good low resistance contact with external circuitries
Claims 10-13, and 45-46 are rejected under 35 U.S.C. 103 as obvious over Gatterbauer et al. (Pub. No.: US 2020/0111754 A1), as applied to claim 1 and claim 44, respectively.
Regarding Claim 10, Gatterbauer et al., as applied to claim 1, discloses
the semiconductor device, wherein the first intermediate layer is formed on an interlayer dielectric layer (Par. 0024).
Gatterbauer et al. does not explicitly disclose
the semiconductor device, wherein the semiconductor device further comprises an ohmic contact on the semiconductor die, and wherein the semiconductor device further comprises a conductive via that electrically connects the first metal contact layer and the ohmic contact. The Examiner takes OFFICIAL NOTICE that the semiconductor device, wherein the semiconductor device further comprises an ohmic contact on the semiconductor die, and wherein the semiconductor device further comprises a conductive via that electrically connects the first metal contact layer and the ohmic contact is well known in the art (in order to establish electrical connections between conductors of different levels). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the semiconductor device, wherein the semiconductor device further comprises an ohmic contact on the semiconductor die of Gatterbauer et al., and wherein the semiconductor device further comprises a conductive via that electrically connects the first metal contact layer and the ohmic contact in order to establish electrical connections between conductors of different levels.
Regarding Claim 11, modified Gatterbauer et al., as applied to claim 10, discloses
the semiconductor device, wherein the intermediate layer and the first metal contact layer extend into the conductive via (obvious in light of rejection of claim 10 made above).
Regarding Claim 12, modified Gatterbauer et al., as applied to claim 10, discloses
the semiconductor device, wherein the conductive via comprises a conductive plug (obvious in light of rejection of claim 10 made above).
Regarding Claim 13, modified Gatterbauer et al., as applied to claim 12, discloses
the semiconductor device, wherein the conductive plug comprises tungsten (Gatterbauer et al. - Par. 0024 in light of the rejection of claim 12 made above).
Regarding Claim 45, Gatterbauer et al., as applied to claim 44, discloses
the semiconductor device, further comprising an interlayer dielectric layer on the semiconductor die, wherein the metal layer structure is on the interlayer dielectric layer; wherein the intermediate layer is between the interlayer dielectric layer and the metal contact layer (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D).
Gatterbauer et al. does not explicitly disclose
the semiconductor device, wherein the semiconductor device further comprises an ohmic contact on the semiconductor die, and wherein the semiconductor device further comprises a conductive via through the interlayer dielectric layer that electrically connects the metal layer structure and the ohmic contact. The Examiner takes OFFICIAL NOTICE that the semiconductor device, wherein the semiconductor device further comprises an ohmic contact on the semiconductor die, and wherein the semiconductor device further comprises a conductive via that electrically connects the first metal contact layer and the ohmic contact is well known in the art (in order to establish electrical connections between conductors of different levels). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the semiconductor device, wherein the semiconductor device further comprises an ohmic contact on the semiconductor die of Gatterbauer et al., and wherein the semiconductor device further comprises a conductive via through the interlayer dielectric layer that electrically connects the metal layer structure and the ohmic contact in order to establish electrical connections between conductors of different levels.
Regarding Claim 46, modified Gatterbauer et al., as applied to claim 44, discloses
the semiconductor device, wherein the intermediate layer and the metal contact layer extend into the conductive via (obvious in light of rejection of claim 45 made above).
Claim 16 is rejected under 35 U.S.C. 103 as obvious over Gatterbauer et al. (Pub. No.: US 2020/0111754 A1), as applied to claim 1, in view of Hilsenbeck et al. (Pub. No.: US 2016/0155714 A1).
Regarding Claim 16, Gatterbauer et al., as applied to claim 1, discloses the semiconductor device, wherein the first metal contact layer comprises copper or aluminum or an aluminum alloy (Par. 0024).
Gatterbauer et al. does not explicitly disclose the semiconductor device, wherein the first metal contact layer comprises aluminum copper
However, Hilsenbeck et al., at least implicitly teaches
the semiconductor device, wherein the first metal contact layer comprises aluminum copper (Par. 0088; Figs. 7A-7E). In short, use of copper, aluminum and aluminum copper as a material for a metal contact layer have been documented before the effective filing date of the instant application. Gatterbauer et al. discloses the claimed invention except for the semiconductor device, wherein the first metal contact layer comprises aluminum copper. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor device, wherein the first metal contact layer comprises aluminum copper, since it has been held that the simple substitution of one known element for another to obtain predictable results is obvious.
Claims 35-42 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Gatterbauer et al. (Pub. No.: US 2020/0111754 A1), or, in the alternative, under 35 U.S.C. 103 as obvious over Gatterbauer et al. (Pub. No.: US 2020/0111754 A1).
Regarding Claim 35, Gatterbauer et al. discloses a semiconductor device, comprising: a semiconductor die (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – semiconductor die comprising substrate 104 or substrate together with interlevel dielectric 104); and a metal contact structure on the semiconductor die, the metal contact structure comprising a first metal layer structure on the semiconductor die and a second metal layer structure on the first metal layer structure (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – metal contact structure comprising a first metal layer structure comprising layers 100 (structured interlayer) and 108 (structured metallization); although this prior art does not explicitly disclose the metal contact structure further comprising a second metal layer structure on the first metal layer structure, its presence is implied; in IC industry, a device is generally formed of quite a few levels of metallization layers; this prior art shows one of the levels and does not mention other levels; however, it is understood that the teachings of this prior art to suppress propagation of cracks is equally applicable to other levels);
PNG
media_image1.png
622
564
media_image1.png
Greyscale
wherein the first metal layer structure comprises an intermediate layer on the semiconductor die and a first metal contact layer on the intermediate layer (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – first metal layer structure comprising intermediate layer 100 (structured interlayer) and first metal contact layer 108 (structured metallization)); wherein an outer edge of the first metal contact layer is inset from an outer edge of the intermediate layer so that a peripheral portion of the intermediate layer extends farther outward than the outer edge of the first metal contact layer (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D); wherein the metal contact structure further comprises a protective layer on the peripheral portion of the first metal contact layer and the outer edge of the intermediate layer (Par. 0046-0050; Fig. 9D – protective layer 908 (barrier)); wherein the second metal layer structure extends at least partially over the protective layer (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – as mentioned above, although this prior art does not explicitly disclose the metal contact structure further comprising a second metal layer structure on the first metal layer structure, its presence is implied; in IC industry, a device is generally formed of quite a few levels of metallization layers; this prior art shows one of the levels and does not explicitly mention presence of other levels; however, it is understood that there are others levels above in order to make contact with external circuitries; so if there is a second metal layer structure which is on a higher level the first metal structure, it would naturally extend at least partially over the protective layer).
In the alternative, assuming arguendo that Gatterbauer et al. is not emphatic enough regarding the semiconductor device, comprising: the metal contact structure comprising a second metal layer structure on the first metal layer structure; and wherein the second metal layer structure extends at least partially over the protective layer, The Examiner takes OFFICIAL NOTICE that in IC industry, a device is generally formed of quite a few levels of metallization layers; this prior art shows one of the levels and does not mention other levels; however, it is understood that the teachings of this prior art to suppress propagation of cracks is equally applicable to other levels; in a typical IC backend of line (BEOL) metal stack, the metal contact structures adapted in different levels of a device have many similarities to each other. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the semiconductor device, comprising: the metal contact structure comprising a second metal layer structure on the first metal layer structure; and wherein the second metal layer structure extends at least partially over the protective layer of Gatterbauer et al. in order to make good low resistance contact with external circuitries
Regarding Claim 36, Gatterbauer et al., as applied to claim 35, discloses
the semiconductor device, wherein the protective layer comprises a passivation layer on the peripheral portion of the first metal contact layer and the outer edge of the intermediate layer (Par. 0046-0050; Fig. 9D – protective layer 908 (barrier) formed of SiN, SiO, SiCN etc. also acts as a passivation layer).
Regarding Claim 37, Gatterbauer et al., as applied to claim 36, discloses
the semiconductor device, further comprising a polyimide layer on the passivation layer, wherein the second metal structure extends at least partially over the polyimide layer (Par. 0050; Fig. 9D – polyimide layer 910).
Regarding Claim 38, Gatterbauer et al., as applied to claim 35, discloses
the semiconductor device, wherein the protective layer comprises a polyimide layer on the peripheral portion of the first metal contact layer and the outer edge of the intermediate layer (Par. 0050; Fig. 9D – polyimide layer 910).
Regarding Claim 39, Gatterbauer et al., as applied to claim 35, at least implicitly discloses
the semiconductor device, wherein the intermediate layer comprises a first intermediate layer, the second metal layer structure comprises a second intermediate layer on the first metal contact layer and a second metal contact layer on the second intermediate layer (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – first intermediate layer 100 (structured interlayer); although this prior art does not explicitly disclose the second metal layer structure comprises a second intermediate layer on the first metal contact layer and a second metal contact layer on the second intermediate layer, its presence is implied; in IC industry, a device is generally formed of quite a few levels of metallization layers; this prior art shows one of the levels and does not explicitly mention presence of other levels; however, it is understood that there are others levels above in order to make contact with external circuitries).
In the alternative, assuming arguendo that Gatterbauer et al. is not emphatic enough regarding the semiconductor device, wherein the second metal layer structure comprises a second intermediate layer on the first metal contact layer and a second metal contact layer on the second intermediate layer, The Examiner takes OFFICIAL NOTICE that in a typical IC backend of line (BEOL) metal stack, the metal contact structures adapted in different levels of a device have many similarities to each other. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the semiconductor device, wherein the intermediate layer comprises a first intermediate layer, the second metal layer structure comprises a second intermediate layer on the first metal contact layer of Gatterbauer et al. and a second metal contact layer on the second intermediate layer in order to make good low resistance contact with external circuitries.
Regarding Claim 40, modified Gatterbauer et al., as applied to claim 39, discloses
the semiconductor device, wherein the first intermediate layer and the second intermediate layer comprise titanium nitride, titanium tungsten and/or tantalum nitride (Gatterbauer et al. - Par. 0024, 0048 in light of rejection of claim 39).
Regarding Claim 41, modified Gatterbauer et al., as applied to claim 40, discloses
the semiconductor device, wherein the first intermediate layer comprises titanium nitride and the second intermediate layer comprises titanium tungsten (Gatterbauer et al. - Par. 0024, 0048 in light of rejection of claim 7; the primary reference teaches that the first intermediate layer comprises titanium nitride and/or titanium tungsten; modified Gatterbauer et al. teaches the first intermediate layer and the second intermediate layer comprise titanium nitride, and/or titanium tungsten; which particular materials are chosen for the different intermediate layers would depend on the type and amount of stress that would get generated due to the deposition of the first and second contact layers).
Regarding Claim 42, modified Gatterbauer et al., as applied to claim 40, discloses
the semiconductor device, wherein the first metal contact layer and the second metal contact layer comprise copper, and wherein the first intermediate layer and the second intermediate layer comprise titanium tungsten (Gatterbauer et al. - Par. 0024 in light of rejection of claim 7).
Claim 43 is rejected under 35 U.S.C. 103 as obvious over Gatterbauer et al. (Pub. No.: US 2020/0111754 A1), as applied to claim 35.
Regarding Claim 43, Gatterbauer et al., as applied to claim 35, discloses
the semiconductor device, wherein the first intermediate layer is formed on an interlayer dielectric layer (Par. 0024).
Gatterbauer et al. does not explicitly disclose
the semiconductor device, wherein the semiconductor device further comprises an ohmic contact on the semiconductor die, and wherein the semiconductor device further comprises a conductive via that electrically connects the first metal contact layer and the ohmic contact. The Examiner takes OFFICIAL NOTICE that the semiconductor device, wherein the semiconductor device further comprises an ohmic contact on the semiconductor die, and wherein the semiconductor device further comprises a conductive via that electrically connects the first metal contact layer and the ohmic contact is well known in the art (in order to establish electrical connections between conductors of different levels). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the semiconductor device, wherein the semiconductor device further comprises an ohmic contact on the semiconductor die of Gatterbauer et al., and wherein the semiconductor device further
comprises a conductive via that electrically connects the first metal contact layer and the ohmic contact in order to establish electrical connections between conductors of different levels.
Claim 51 is rejected under 35 U.S.C. 102(a)(1) as anticipated by Gatterbauer et al. (Pub. No.: US 2020/0111754 A1), as applied to claim 44, or, in the alternative, under 35 U.S.C. 103 as obvious over Gatterbauer et al. (Pub. No.: US 2020/0111754 A1), as applied to claim 44.
Regarding Claim 51, Gatterbauer et al., as applied to claim 44, at least implicitly discloses
the semiconductor device, wherein the intermediate layer comprises a first intermediate layer, the metal layer structure further comprising a second metal layer structure on the first metal layer structure, the second metal layer structure comprising a second intermediate layer on the first metal contact layer and a second metal contact layer on the second intermediate layer (Par. 0023-0029, 0040-0050; Figs. 1-4 & 9D – first intermediate layer 100 (structured interlayer); although this prior art does not explicitly disclose the metal contact structure further comprising a second metal layer structure on the first metal layer structure, the second metal layer structure comprising a second intermediate layer on the first metal contact layer and a second metal contact layer on the second intermediate layer, its presence is implied; in IC industry, a device is generally formed of quite a few levels of metallization layers; this prior art shows one of the levels and does not mention other levels; however, it is understood that the teachings of this prior art to suppress propagation of cracks is equally applicable to other levels).
In the alternative, assuming arguendo that Gatterbauer et al. is not emphatic enough regarding the semiconductor device, wherein the metal layer structure further comprising a second metal layer structure on the first metal layer structure, the second metal layer structure comprising a second intermediate layer on the first metal contact layer and a second metal contact layer on the second intermediate layer, The Examiner takes OFFICIAL NOTICE that in a typical IC backend of line (BEOL) metal stack, the metal contact structures adapted in different levels of a device have many similarities to each other. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the semiconductor device, wherein wherein the metal layer structure further comprising a second metal layer structure on the first metal layer structure of Gatterbauer et al., the second metal layer structure comprising a second intermediate layer on the first metal contact layer and a second metal contact layer on the second intermediate layer in order to suppress propagation of cracks in other metal levels too.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Rueb et al. (Pub. No.: US 2005/0179068 A1) – This prior art teaches a semiconductor device, comprising: a semiconductor die (1); and a metal contact structure on the semiconductor die, the metal contact structure comprising a first metal layer structure on the semiconductor die; wherein the first metal layer structure comprises an intermediate layer (3) and a first metal contact layer (4) on the intermediate layer (3); wherein an outer edge of the first metal contact layer is inset from an outer edge of the intermediate layer so that a peripheral portion of the intermediate layer extends farther outward than the outer edge of the first metal contact layer (Par. 0045-0049; Fig. 1A-1F).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED I GHEYAS whose telephone number is (571)272-0592. The examiner can normally be reached on Monday-Friday from 8:30 AM - 5:30 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley, can be reached at telephone number (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
08/03/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
Prosecution Insights