DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/23/2026 has been entered.
This action is responsive to the amendment filed on 3/23/2026. Claims 1-14 are pending and have been examined. Claims 1-3, 7 and 9-12 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 9-10 and 12-14 are objected to because of the following informalities:
In regards to claim 9, lines 16-17 delete “operation code” as it appears it was left in the amended claim erroneously.
In regards to claim 10, line 1 amend the limitation to state “The method of reducing processor stall latency [[in transfer]] during execution of custom instructions” as to use language consistent with claim 9, lines 1-2.
In regards to claim 12, line 22 delete the period after “convenience” to correct a grammatical issue, as a period should come at end of claim/sentence.
In regards to claim 13, line 1 amend the limitation to state “The method of reducing processor stall latency [[in transfer]] during execution of custom instructions” as to use language consistent with claim 9, lines 1-2.
In regards to claim 14, line 1 amend the limitation to state “The method of reducing processor stall latency [[in transfer]] during execution of custom instructions” as to use language consistent with claim 9, lines 1-2.
Claims 10 and 13-14 are dependent upon claim 9 above and therefore are similarly objected to for including the deficiencies of claim 9 above.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In regards to claim 1, the limitation stating “…wherein the custom instruction extension is configured to decode the operation code to…” fails to comply with the written description requirement because the original disclosure does not properly describe a custom instruction extension decoding an operation code to determine an execution mode in sufficient detail that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Specifically, page 10, lines 3-24 to page 11, lines 1-9 discloses using blocking and non-blocking implementations when executing instructions using a hardened processor based on operation code, however, the disclosure does not discuss any decoding performed by a custom instruction extension. While, the disclosure mentions the hardened processor operating in a blocking or non-blocking implementation based on an operation code, the disclosure does not discuss the implementations occurring in light of decoding performed by a custom instruction extension. In fact, nowhere in the specification discusses the custom instruction extension having any decode capabilities. Thus, the specification does not provide sufficient support for the claim limitation discussed above.
Claim 9 is similarly rejected on the same basis as claim 1 above.
Claims 2-8, 10 and 13-14 are dependent upon one of the claims above and therefore are similarly rejected on the same basis as one of the claims above.
In regards to claim 11, the limitation stating “…performing non-blocking implementation, in response to said operation code being a second predetermined operation code; wherein said non-blocking implementation comprises: a. freeing said hardened processor; b. sending said R-type instructions, by said first memory system, to said custom accelerator; c. processing of said R-type instructions by said custom accelerator…” fails to comply with the written description requirement because the original disclosure does not properly describe performing a non-blocking implementation in response to said operation code being a second predetermined operation code in sufficient detail that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
Specifically, page 10, lines 3-24 and Fig. 3 discloses implementing a blocking and non-blocking implementation based on a first operation code (0xB) in which a non-blocking implementation follows the no path of Fig. 3. While, a second predetermined opcode (0x5B) is discussed regarding Fig. 4 and details based on the opcode the custom instruction extension receives a response from the second memory system and returns the response to an application. However, the disclosure does not discuss implementing the non-blocking implementation based on the second predetermined opcode nor freeing the hardened processor in such a mode based on the second predetermined operation code. Rather, page 10, lines 3-24 to page 11, lines 1-9 disclose a non-blocking implementation which occurs based on said first predetermined operation code, wherein the non-blocking implementation frees the hardened processor; while a second predetermined opcode, as illustrated in Fig. 4, causes the custom instruction extension to retrieve a response signal from a second queue and return the response to the application. (Examiner also notes that page 6, lines 15-20 detail the differences in Figs. 3-4 as it states Fig. 3 discusses a waiting for response signals from the custom accelerator and Fig. 4 discusses retrieving response from the custom accelerator).
Thus, the specification does not provide sufficient support for the claim limitation discussed above.
Claim 12 is similarly rejected on the same basis as claim 11 above.
Claim Interpretations
Claims 11-12 recite the following contingent limitations: “…waiting by said hardened processor for a response signal from at least one custom accelerator before returning said response signal to said application in response to said operation code being a first predetermined operation code, while returning no signal by said hardened processor to said application in response to said operation code not being said first predetermined operation code; performing non-blocking implementation, in response to said operation code being a second predetermined operation code; wherein said non-blocking implementation comprises: a. freeing said hardened processor; b. sending said R-type instructions, by said first memory system, to said custom accelerator; processing of said R-type instructions by said custom accelerator; and d. storing a corresponding response signal in a second memory system while being accessible by said hardened processor at said hardened processor's convenience...”
The contingent limitation uses the language “in response to” which is contingent because they are only required to be performed if (e.g. in response to) a condition being met (e.g. waiting for a signal or returning no signal depending on if an operation code is a first predetermined operation 0x0B (only on claim 11); or performing a non-blocking implementation if an operation code is a second predetermined operation 0x5B (only in claim 12)). However, if a hardened processor checks operations codes and the processor never encounters the first or second predetermined operation codes the following steps are not required to occur based on the broadest reasonable interpretation given to contingent limitations in method claims (See MPEP 2111.04(II) See Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016)).
The examiner suggests amending the claims to remove the contingent limitations stating “in response” to positively recite each step of the method claim.
Prior Art Considerations
9. The claims are currently subject to 35 USC 112(a) rejections because the scope of the claims lacks support and thus prior art rejections have not been applied. However, the examiner notes that amendments made to overcome the 35 USC 112(a) rejections may change the scope of the claims such that new grounds of prior art rejections may be made.
Response to Arguments
10. Applicant’s arguments, see pages 10-19, filed on 3/23/2026, with respect to the rejection(s) of claim(s) 1-10 and 13-14 under 35 USC 103 and/or 112(b) have been fully considered and are partially persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 USC 112(a) for claims 1-14.
Conclusion
11. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
NPL reference “ENABLING ACCELERATOR-SOC CO-DESIGN USING RISC-V CHIPYARD FRAMEWORK” for teaching using a DMA engine interface for communication between RISC-V processor and accelerator to support clock domain crossing from system clock to accelerator clock
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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