Prosecution Insights
Last updated: July 17, 2026
Application No. 18/612,815

SEMICONDUCTOR DEVICE AND METHODS OF FORMATION

Non-Final OA §103
Filed
Mar 21, 2024
Priority
Mar 13, 2024 — GR 20240100186
Examiner
NGUYEN, DUY T V
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
839 granted / 1065 resolved
+18.8% vs TC avg
Strong +17% interview lift
Without
With
+16.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
58 currently pending
Career history
1125
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
78.8%
+38.8% vs TC avg
§102
4.0%
-36.0% vs TC avg
§112
6.3%
-33.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1065 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Election/Restrictions 1. Applicant’s election without traverse of Group IA, claims 1-7 in the reply filed on 5/19/2026 is acknowledged. Claims 1-14 & 21-26 are pending in the application. Claims 8-14 are withdrawn. Claims 15-20 are cancelled. Claims 21-26 are new. Specification 2. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Appropriate correction is required. Claim Objections 3. The claims are objected because of the following reasons: Re claim 22, line 2: between “greater than” & “approximately” insert –or-- (see specification [0040], “greater than or approximately equal to 4.89 angstroms”). Re claim 23, line 2: delete “approximately” (see specification [0041], “greater than 3.81 angstroms”). Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 4. Claims 1, 2, 21 and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Manfrini et al. (US 2022/0246766) in view of Chen et al. (US 2018/0366375). Re claim 1, Manfrini teaches, under BRI, Figs. 3, 5 & 7, [0017, 0019], a transistor structure, comprising: -a gate electrode (102) [0017]; -a p-type oxide-semiconductor channel layer (106) (e.g. a p-type doped semiconductor or oxide semiconductor, [0019]); and -a gate dielectric layer (104) [0019] between the gate electrode (102) and the p-type oxide-semiconductor channel layer (106). PNG media_image1.png 390 423 media_image1.png Greyscale Manfrini does not explicitly teach wherein a majority of a crystal lattice structure of the p-type oxide-semiconductor channel layer is composed of a (110) crystal phase. Chen teaches, [0057], “For example, the (110) crystal plane has higher atomic density than the (100) crystal plane and hence may be better for a channel in the p-type FET due to the most number of covalent bonds that is better for hole conduction”. As taught by Chen, one of ordinary skill in the art would utilize & modify the above teaching into Manfrini to obtain a majority of a crystal lattice structure of the p-type oxide-semiconductor channel layer is composed of a (110) crystal phase as claimed, because it aids in improving carrier mobility & device performance. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chen in combination Manfrini due to above reason. Re claim 2, Manfrini teaches, under BRI, Fig. 3 & 7, [0019], an interfacial layer (e.g., 106b) between the gate dielectric layer (104) and the p-type oxide-semiconductor channel layer (106a), wherein the interfacial layer (106b) comprises a metal-oxide material (e.g., IGZO). Re claim 21, Manfrini teaches, under BRI, Figs. 3, 5 & 7, [0017, 0019, 0029], a transistor structure, comprising: -a gate electrode (102) [0017]; -a gate dielectric layer (104) [0019] on the gate electrode (102); -an interfacial layer (112a or 106b, Fig. 7, [0029]) on the gate dielectric layer (104); and -a p-type oxide-semiconductor channel layer (106a) (e.g. a p-type doped semiconductor or oxide semiconductor, [0019]) on the interface layer (112), wherein a lattice constant of a crystal lattice structure of the interfacial layer (consider 106b) is greater than or approximately equal to a lattice constant of a crystal phase in a crystal lattice structure of the p-type oxide-semiconductor channel layer (106a) (e.g., based on same material of channel layer). PNG media_image1.png 390 423 media_image1.png Greyscale PNG media_image2.png 249 335 media_image2.png Greyscale Manfrini does not explicitly teach a (110) crystal phase in a crystal lattice strucutre. Chen teaches, [0057], “For example, the (110) crystal plane has higher atomic density than the (100) crystal plane and hence may be better for a channel in the p-type FET due to the most number of covalent bonds that is better for hole conduction”. As taught by Chen, one of ordinary skill in the art would utilize & modify the above teaching into Manfrini to obtain a (110) crystal phase in a crystal lattice structure as claimed, because it aids in improving carrier mobility & device performance. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Chen in combination Manfrini due to above reason. Re claims 24-26, Manfrini/Chen teaches wherein the interfacial layer (106b) has a thickness; the p-type oxide semiconductor layer (106a) has a thickness; and the gate dielectric layer (104) has a thickness. Manfrini/Chen does not explicitly teach the thickness in a rang of approximately 3 nanometers to approximately 30 nanometers; approximately 0.5 nanometers to approximately 30 nanometers; and approximately 100 nanometers. Manfrini teaches, [0020], “a range of between approximately 3 nm and approximately 20 nm.” & “a range of between approximately 1 nanometers (nm) and approximately 15 nm.” It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Manfrini to obtain thickness ranges as claimed, because thickness of layer is known to affect device properties and would depend on the desired device density and the desired device characteristics. One of ordinary skill in the art would have been led to the recited thickness through routine experimentation to achieve desired characteristics of the formed device. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233. 5. Claims 3, 4, 6, 7, 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Manfrini as modified by Chen as applied to claims 1, 2 & 21 above, and further in view of Yu et al. (US 2002/0158245). The teachings of Manfrini/Chen have been discussed above. Re claims 3 & 4, Manfrini/Chen does not explicitly teach wherein the metal-oxide material of the interfacial layer has a greater change in Gibbs free energy than a change in Gibbs free energy of a material of the gate dielectric layer; wherein the metal-oxide material comprises at least one of: calcium oxide (CaO), yttrium oxide (YxOy), lithium oxide (LixO), lanthanum oxide (LaxOy), strontium oxide (SrO), magnesium oxide (MgO), or barium oxide (BaO). Yu teaches the use of metal oxide such as SrO & BaO [0026]. As taught by Yu, one of ordinary skill in the art would utilize & modify the above teaching in Manfrini/Chen to obtain Gibbs free energy difference & material of the metal-oxide material as claimed, because it aids in achieving high quality material in qualify semiconductor structure while exhibiting minimal leakage current. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yu in combination Manfrini/Chen due to above reason. Re claim 6, Manfrini teaches, Figs. 5 & 7, wherein the gate electrode (102) is below the p-type oxide-semiconductor channel layer (consider 106b) in the transistor structure; and wherein the p-type oxide-semiconductor channel layer (106b) is on a top surface of the interfacial layer (consider 106a, 112a). Re claim 7, Manfrini teaches, Figs. 3 & 7, wherein the gate electrode (102) is above the p-type oxide-semiconductor channel layer (consider 106a) in the transistor structure; and wherein the interfacial layer (consider 106b) is on a top surface of the p-type oxide-semiconductor channel layer (106a). Re claims 22 & 23, in combination cited above, Yu teaches, [0026], wherein the lattice constant of the crystal lattice structure of the interfacial layer is greater than approximately equal to 4.89 angstroms; and wherein the lattice constant of the crystal lattice structure of the interfacial layer is greater than approximately 3.81 angstroms (e.g., BaO 5.545 angstroms; SrO 5.160 angstroms). “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). 6. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Manfrini as modified by Chen as applied to claims 1 & 2 above, and further in view of Kurth et al. (US 2016/0274057). The teachings of Manfrini/Chen have been discussed above. Re claim 5, Manfrini/Chen does not teach wherein the metal-oxide material comprises calcium oxide (CaO) doped with strontium (Sr). Kurth teaches the metal-oxide material comprises calcium oxide (CaO) doped with strontium (Sr) (e.g., mixture of CaO & SrO) (claim 12, [0051]). As taught by Kurth, one of ordinary skill in the art would utilize & modify the above teaching into Manfrini/Chen to obtain the metal-oxide material comprises calcium oxide (CaO) doped with strontium (Sr), because it aids in reducing structural defects and improving stability in the formed device. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416. Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kurth in combination Manfrini/Chen due to above reason. Conclusion 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY T NGUYEN/ Primary Examiner, Art Unit 2818 5/30/25
Read full office action

Prosecution Timeline

Mar 21, 2024
Application Filed
Jun 08, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685178
SEMICONDUCTOR STRUCTURE COMPRISING SUB-ALIGNMENT MARKS
3y 8m to grant Granted Jul 14, 2026
Patent 12672318
SEMICONDUCTOR DEVICES INCLUDING BUFFER LAYER STRUCTURE
4y 1m to grant Granted Jun 30, 2026
Patent 12672274
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE
3y 5m to grant Granted Jun 30, 2026
Patent 12672424
SENSOR EMBEDDED DISPLAY PANEL AND ELECTRONIC DEVICE
2y 10m to grant Granted Jun 30, 2026
Patent 12666959
METHOD FOR FORMING SEMICONDUCTOR STRUCTURE INCLUDING CAPACITOR
3y 5m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
96%
With Interview (+16.7%)
2y 8m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1065 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month