DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 5-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 20210183659 A1) hereinafter referred to as “Lin659”.
Regarding claim 1: Lin659 teaches a manufacturing method of a semiconductor structure (abstract), comprising: providing a substrate (Fig. 10B, element 110), wherein the substrate comprises a peripheral region (Fig. 10B, element 114) and a memory region (Fig. 10B, element 112); forming a first isolation structure in the substrate in the peripheral region (Fig. 10B, element 144); after forming the first isolation structure, forming a first floating gate layer (Fig. 10B, element 190’) and a tunneling dielectric layer (Fig. 10B, element 180’) in the memory region (See Figs. 8-11B below and paras. [0024-0026] for the sequence of steps), wherein the first floating gate layer is located on the substrate, and the tunneling dielectric layer is located between the first floating gate layer and the substrate (See at least Fig. 10B); and after forming the first floating gate layer and the tunneling dielectric layer, forming a second isolation structure in the substrate in the memory region (Fig. 11B, elements 222).
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Figs. 8-11B taken from Lin659: First isolation structure (Fig. 8, element 144) is formed in the peripheral region (Fig. 8, element 114) before forming a first floating gate layer (Fig. 10B, element 190’) and a tunneling dielectric layer (Fig. 10B, element 180’) in the memory region (Fig. 10B, element 112). Lastly, the second isolation structures (Fig. 11B, elements 222) are formed in the memory region (Fig. 11B, element 112).
Regarding claim 5: Lin659 teaches the manufacturing method of the semiconductor structure according to claim 1, wherein a method of forming the first floating gate layer (Fig. 10B, element 190’) and the tunneling dielectric layer (Fig. 10B, element 180’) comprises: sequentially forming a dielectric material layer (Fig. 10B, element 180), a floating gate material layer (Fig. 10B, element 190), and a hard mask layer (Fig. 10B, element 210) on the substrate (See paras. [0026-0027], “In the present embodiments, a floating gate film 190 is conformally formed over the structure in FIG. 8 (i.e., over the tunneling film 180”, “After the formation of the floating gate film 190, another pad layer 200 is conformally formed over the floating gate film 190, and another hard mask layer 210 is conformally formed over the pad layer 200”); and patterning the hard mask layer, the floating gate material layer, and the dielectric material layer in the memory region to form a patterned hard mask layer (Fig. 10B, element 210’), the first floating gate layer (Fig. 10B, element 190’), and the tunneling dielectric layer (Fig. 10B, element 180’).
Regarding claim 6: The manufacturing method of the semiconductor structure according to claim 5, wherein a method of forming the second isolation structure comprises: patterning the substrate in the memory region to form a trench in the substrate (Fig. 10B, element 112T); and forming the second isolation structure in the trench (Fig. 11B, elements 222).
Regarding claim 7: Lin659 teaches the manufacturing method of the semiconductor structure according to claim 5, wherein the second isolation structure (Fig. 11B, elements 222) is located on a sidewall of the tunneling dielectric layer (Fig. 11B, element 180’) and a sidewall of the first floating gate layer (Fig. 11B, element 190’, the side walls of the tunneling layer and the floating gate layer are in contact with the isolation structure).
Regarding claim 8: Lin659 teaches the manufacturing method of the semiconductor structure according to claim 5, further comprising: forming a patterned photoresist layer (“For example, a photoresist layer is formed on the hard mask layer 210 (referring to FIG. 9) and then patterned by photolithography processes”, para. [0029]) wherein the patterned photoresist layer covers the first isolation structure (See Fig. 9, the hard mask 210 is coated with photoresist and located over first isolation structure element 144); performing an etch back process on the second isolation structure by using the patterned photoresist layer as a mask to reduce a height of the second isolation structure; (See Figs. 10B-12A) removing the patterned photoresist layer; and removing the patterned hard mask layer (See Fig. 13A).
Regarding claim 9: Lin659 teaches the manufacturing method of the semiconductor structure according to claim 8, wherein a top surface of the second isolation structure is higher than a bottom surface of the first floating gate layer and lower than a top surface of the first floating gate layer. (See Fig. 14A, “After the recessing, the floating gate film 190′ protrudes from a top surface of the isolation features 222 and 226. Recessing the isolation features 222 may enhance a coupling ratio between floating gates and control gates that are subsequently formed.”, para. [0038])
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. US (20110281415 A1) hereinafter referred to as “Kang415” in view of Lee (US 20070026633 A1) hereinafter referred to as “Lee633”.
Regarding claim 1: Kang415 teaches a manufacturing method of a semiconductor structure (abstract), comprising: providing a substrate (See at least Fig. 19, element 200), wherein the substrate comprises a peripheral region (Fig. 19, element B) and a memory region (Fig. 19, element A); forming a first isolation structure in the substrate in the peripheral region (Fig. 19, elements 245, 268, and 292); forming a first floating gate layer (Fig. 11, element 222) and a tunneling dielectric layer (Fig. 11, element 212) in the memory region, wherein the first floating gate layer is located on the substrate, and the tunneling dielectric layer is located between the first floating gate layer and the substrate (See at least Fig. 11); and after forming the first floating gate layer and the tunneling dielectric layer, forming a second isolation structure in the substrate in the memory region (See at least Fig. 16). Kang415 does not explicitly teach that the first isolation structure is formed before the tunneling dielectric layer and floating gate layer are formed.
Lee633 teaches that isolation structures in the peripheral region and the memory region of a semiconductor memory device can be formed independently (“A semiconductor device comprising a trench device isolation layer and a method for fabricating the semiconductor device are disclosed. The method comprises forming a plurality of first trenches on a first region of a semiconductor substrate, filling the first trenches with a first insulation material to form first device isolation layers, forming a plurality of second trenches on a second region of the semiconductor substrate, and filling the second trenches with a second insulation material different from the first insulation material to form second device isolation layers, wherein the first trenches and the second trenches are formed using different respective processes.”, abstract) and that such a process may be desirable in semiconductor memory devices (“Trenches formed in a cell array region of a semiconductor memory device may have different depths than trenches formed in a peripheral circuit region of a semiconductor memory device. However, properly forming device isolation layers in the trenches may be more problematic when the depths of the trenches are different. In addition, when the aspect ratio of a trench is relatively great, it is more difficult to fill the inside of the trench with a device isolation layer without forming a void in the device isolation layer.”, para. [0006], “A void 11 may be formed in a specific region of device isolation layers 40b, 40c, and 40d of peripheral region B (e.g., in a device isolation layer having a relatively large aspect ratio, or in a region where trenches cross). A void 11 may occur because all of the trenches are filled with the same insulation material without regard to the different shapes and aspect ratios of the trenches. Moreover, when an insulation material that is only useful for filling trenches formed in cell array region A is used to fill the trenches formed in peripheral circuit region B, voids 11 will unavoidably be formed in the trenches of peripheral circuit region B that have relatively large aspect ratios. Thus, difficulties arise when the trenches of cell array region A and the trenches of peripheral circuit region B are filled simultaneously.”, para. [0010]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to use the teachings of Lee633 to modify the manufacturing method disclosed in Kang415 to form the first isolation structure before the tunneling dielectric and floating gate layers. For example, by including a step forming a hard mask and etching the isolation trenches for the first isolation structure then depositing the isolation material in the first isolation trench, one could arrive at the claimed invention with a reasonable expectation of success.
Regarding claim 2: In addition to the reasoning used to reject claim 1, Kang415 teaches a method of forming the first isolation structure that comprises: sequentially forming a dielectric material layer (Fig. 11, element 214), a floating gate material layer (Fig. 11, element 224), and a hard mask layer (Fig. 11, element 234) on the substrate; patterning the hard mask layer and the floating gate material layer in the peripheral region to form a patterned hard mask layer and a patterned floating gate material layer in the peripheral region (See Fig. 11); and forming the first isolation structure (See at least Fig. 19, elements 245, 268, and 292); in the trench. Kang415 does not explicitly teach conformally forming a spacer material layer on the patterned hard mask layer, the patterned floating gate material layer, and the dielectric material layer; patterning the spacer material layer, the dielectric material layer, and the substrate to form a spacer and to form a trench in the substrate, wherein the spacer is located on a sidewall and a top surface of the patterned hard mask layer and is located on a sidewall of the patterned floating gate material layer and removing the spacer. However, Kang415 teaches that (“Referring to FIG. 10, the hard mask layer 230 may be patterned by a photolithography process to form first and second hard masks 232 and 234. The floating gate layer 220 and the tunnel insulation layer 210 may be patterned using the first and the second hard masks 232 and 234 as etching masks to form a first floating gate 222 and a first insulation layer pattern 212 in the first region A and a second floating gate 224 and a second insulation layer pattern 214 in the second region B.”, para [0071]) implying that a photoresist pattern is applied before the photolithography process.
Lee633 teaches using a photoresist pattern to etch the floating gate layer (“Referring to FIG. 10, an etching process is then performed using a photoresist pattern PR as an etching mask, and top portions of second device isolation layers 170 and a portion of a top portion of a least one first device isolation layer 140 is thereby removed. Second device isolation layers 170 disposed between floating gate electrodes 184 are etched (i.e., recessed) to expose sides of floating gate electrodes 184. Thus, the exposed surface area of each of floating gate electrodes 184 increases, so a coupling ratio between each floating gate electrode 184 and a control gate electrode (which will be formed subsequently) increases. In addition, since high-density plasma CVD oxide, from which first device isolation layers 140 are formed, may be etched at a lower rate compared to USG oxide, from which second device isolation layers 170 are formed, the first device isolation layer 140 formed on a boundary between cell array region A and peripheral circuit region B may not be etched as deeply as second device isolation layers 170 formed in cell array region A.” para. [0038]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to use a photoresist pattern, as taught by Lee633, before etching using the lithography process disclosed in Kang415 to arrive at the claimed invention with a reasonable expectation of success. The examiner notes that the specification in the instant case does not describe what the spacer material layer is made out of or its purpose, only that it may be removed by a wet-etching method, therefore any prior art that includes the use of photoresist or a hard mask to pattern the first isolation trenches could potentially read on the claim limitation of depositing and removing the spacer material layer in claim 2.
Regarding claim 4: In addition to the reasoning used to reject claim 2 based on the teachings of Kang415 and Lee633, Kang415 teaches the manufacturing method of the semiconductor structure wherein the first isolation structure (See at least Fig. 19, elements, 245, 268, and 292) is located on the sidewall of the patterned floating gate material layer (See at least Figs. 17-18, elements 292 are in contact with the side wall of element 224, which is part of the second floating gate pattern) and the hard mask pattern (In the example embodiment the hard mask pattern (See at least Fig 13, element 234 is removed, however it is disclosed in the specification that this is optional, “The first and the second hard mask patterns 232 and 234 may be removed.”, para. [0087]).
Claim 3 is rejected under 35 U.S.C. 103 as being unp3atentable over Kang et al. (20110281415 A1) hereinafter referred to as “Kang415” in view of Lee (US 20070026633 A1) hereinafter referred to as “Lee633” and Lee et al. (US 20210134980 A1) hereinafter referred to as “Lee980”.
Regarding claim 3: In addition to the reasoning used to reject claim 2 on the teachings of Kang415 and Lee633, Kang415 does not explicitly teach that in the process of removing the spacer, simultaneously removing a portion of the dielectric material layer located directly below the spacer. Lee980 teaches that a photoresist or hard mask layer (second hard patterns 110’) can be removed simultaneously with the dielectric material layer (gate dielectric layer) during the etching step (“In some embodiments, the second hard patterns 110′ are entirely consumed during the etching of the semiconductor substrate 102 thereby exposing the first hard mask patterns 108′., para. [0026]”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention that it is possible to remove a photoresist or a hard mask pattern entirely while simultaneously etching a layer below it. This is simply combining prior art elements according to known methods to yield predictable results.
Claims 10-15 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20210183659 A1) hereinafter referred to as “Lin659” in view of Shimizu (US 20020117706 A1) hereinafter referred to as “Shimizu706”).
Regarding claim 10: Lin659 does not teach forming a second floating gate layer on the first floating gate layer.
Shimizu706 teaches forming a second floating gate layer (See at least Fig. 14, element 7) (“By stacking the third conductive film on the first conductive film as mentioned above, the floating gate electrode can be formed in a stacked structure of the conductive films. Furthermore, by forming the first and third conductive films separately, the first and third conductive films can be formed to a desired thickness, while a good state of an interface with other elements in contact with the first and third conductive films can be kept. Still further, by adjusting concentration of the impurity to be doped into the first and third conductive films properly, a desired resistance value of the floating gate electrode can be attained. In addition, since the third conductive film extends over the second insulating film, the surface area of the third conductive film can be made greater than the surface area of the first conductive film, and the surface area of the floating gate electrode can be increased. Therefore, the coupling ratio of the floating gate electrode to control gate electrode can be improved.”, para. [0045])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of the device disclosed in Lin659 to include a second floating gate layer with a reasonable expectation of success, since there is a motivation to tune a desired resistance value of the floating gate electrode taught by Shimizu706.
Regarding claim 11: Lin659 does not teach that the second floating gate layer is greater than a width of the first floating gate layer.
Shimizu706 teaches that the second floating gate layer is formed separately and can be formed to a desired width (since the third conductive film extends over the second insulating film, the surface area of the third conductive film can be made greater than the surface area of the first conductive film, and the surface area of the floating gate electrode can be increased. Therefore, the coupling ratio of the floating gate electrode to control gate electrode can be improved.”, para. [0045]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of the device disclosed in Lin659 to include a second floating gate layer that has a greater width than the first floating gate layer with a reasonable expectation of success, since there is a motivation to improve the coupling ratio of the floating gate electrode to control gate electrode taught by Shimizu706.
Regarding claim 12: Shimizu706 teaches that a portion of the second floating gate layer is located on the second isolation structure. (See at least Fig. 14, the examiner interprets “on” to mean anywhere above the second isolation structure).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of the device disclosed in Lin659, where the floating gate structure is on the second isolation structure, to include a second floating gate layer with a reasonable expectation of success, since there is a motivation to tune a desired resistance value of the floating gate electrode taught by Shimizu706.
Regarding claim 13: Shimizu706 teaches a method of forming the second floating gate layer comprising: forming a floating gate material layer on the first floating gate layer; and patterning the floating gate material layer to form the second floating gate layer and an opening. (“Then, as shown in FIG. 13, a photoresist 24 covering the peripheral circuit portion is formed by photolithography, and using photoresist 24 as a mask, insulating film 9 and doped polysilicon film 6 are dry-etched. Thus, floating gate electrode 8 in the memory cell portion is formed.” para. [0094]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed in Lin659 to form the second floating gate electrode by depositing a second floating gate material layer on the first floating gate material layer and patterning the layers to form an opening, this is a routine and well known method in the semiconductor manufacturing industry.
Regarding claim 14: Shimizu706 teaches that the floating gate material layer is patterned by a lithography process and an etching process. (“Then, as shown in FIG. 13, a photoresist 24 covering the peripheral circuit portion is formed by photolithography, and using photoresist 24 as a mask, insulating film 9 and doped polysilicon film 6 are dry-etched. Thus, floating gate electrode 8 in the memory cell portion is formed.”, para. [0094])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed in Lin659 to form the second floating gate electrode by depositing a second floating gate material layer on the first floating gate material layer and patterning the layers to form an opening using lithography and dry-etching, this is a routine and well known method in the semiconductor manufacturing industry.
Regarding claim 15: claim 15 is rejected in the same manner as claim 14.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20210183659 A1) hereinafter referred to as “Lin659” in view of Shimizu (US 20020117706 A1) hereinafter referred to as “Shimizu706”) and Chuang et al. (US 20220367496 A1) hereinafter referred to as Chuang496.
Regarding claim 16: Lin659 does not teach forming a control gate on the second floating gate layer and in the opening; and forming a dielectric layer between the control gate and the second floating gate layer. Shimizu706 teaches forming a second floating gate layer and a control gate layer, but does not teach forming the control gate layer so that it fills the opening or explicitly state that the layers are separated by a dielectric layer. Chuang449 teaches forming an opening next to the floating gate layer (See Figs. 1M-1N, floating gate layer 104, dielectric layer 152, control gate layer 154) and forming a control gate layer to fill the opening separated by a dielectric material (“With reference to FIG. 1N, the conductive layer 144 and the hard mask layer 106 of the cell region R1 are removed. Then, a part of the isolation structure 101b in the cell region R1 is removed, so that a top surface of a remaining isolation structure 101b is lower than a top surface of the conductive layer 104. Afterwards, an inter-gate dielectric layer 152 is formed in the cell region R1. The inter-gate dielectric layer 152 is, for example, silicon oxide, silicon nitride, or a combination thereof. According to one embodiment, the inter-gate dielectric layer 152 includes silicon oxide/silicon nitride/stacked silicon oxide layer. Afterwards, a conductive layer 154 is formed on the inter-gate dielectric layer 152. The conductive layer 154 serves as a control gate, and a material thereof is, for example, polysilicon. The formation method of the conductive layer 154 is, for example, forming a conductive material layer in the cell region R1 and the peripheral region R2 of the substrate 100, and then patterning the conductive material layer through a photolithography and etching process.”)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to substitute the method of forming the control gate layer in Shimizu706 with the method disclosed Chuang496 to arrive at the claimed invention. The method taught by Chaung496 was well known in the art and such a substitution would have predictable results.
Claims 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al (US 20210183659 A1) hereinafter referred to as “Lin659” in view of Pham et al. (US 20060134845 A1) hereinafter referred to as “Pham845”.
Regarding claim 17: Lin659 does not explicitly teach forming a first gate dielectric layer on the substrate in the peripheral region; forming a second gate dielectric layer on the substrate in the peripheral region, wherein the first gate dielectric layer and the second gate dielectric layer are separated from each other, and a thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer.
Pham845 teaches that the peripheral region may contain a high voltage region and a low voltage region and that each region may have a gate dielectric layer of different thicknesses. (“A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in the peripheral regions according to the voltages of the circuits in these regions. A conductive layer is formed over the memory array and the peripheral circuits to form control gates in the memory array and form gate electrodes in the peripheral regions.”, abstract).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed in Lin659 to form masks over the substrate and deposit dielectric materials of various thicknesses in the peripheral region to arrive at the claimed invention. One would be motivated to do this based on the teachings of Pham 845 to account for differing voltages in portions of the peripheral region.
Regarding claim 18: Pham845 teaches forming a gate material layer (See at least Fig. 9, element 970) on the first gate dielectric layer (See at least Fig. 9, element 640) and the second gate dielectric layer (See at least Fig. 9, element 860).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20210183659 A1) hereinafter referred to as “Lin659” in view of Park et al. (US 20100093173 A1) hereinafter referred to as “Park173”).
Regarding claim 19: Lin659 does not teach that a depth of the first isolation structure located in the substrate is greater than a depth of the second isolation structure located in the substrate.
Park173 teaches a method of forming trenches in the substrate in two different areas of the device that have different depths “a method in the fabrication of a semiconductor device which includes forming a hard mask layer on a substrate, forming a mold mask pattern having a plurality of first topographic features on the hard mask layer in a first area of the device, forming a first mask pattern on the hard mask layer in a second area of the device, forming first spacers which cover the side walls of the first topographic features of the mold mask pattern in the first area, subsequently removing the first topographic features, etching the hard mask layer using the first spacers in the first area as an etch mask while removing the hard mask pattern from the hard mask layer in the second area to thereby form a plurality of first transcribed topographic features in the first area, forming an opening-fabricating mask pattern that covers the first transcribed topographic features in the first area and defines an opening in the second area, etching the substrate in the second area using the opening-fabricating mask pattern as an etch mask to thereby form a trench in the second area, removing the opening-fabricating mask pattern, and simultaneously etching the substrate in the first and second areas using the first transcribed topographic features in the first area as an etch mask to form a plurality of narrow trenches in the substrate in the first area while at the same time increasing the depth of the trench in the substrate in the second area.”, para. [0008]). Park173 also teaches that the trenches may have different widths to improve the integration of the semiconductor device “A typical semiconductor device has patterns formed on several levels on a semiconductor substrate. Photolithography is a well known process used for forming the patterns. Large-scale integration (LSI) semiconductor devices may require different patterns on the same basic level, e.g., patterns whose features have different widths. Also, some LSIs require a pattern whose features have widths so fine that the pattern can not be formed using only photolithography due to limits in the resolution of the photolithography process.”, para. [0002]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed in Lin659, using the method taught by Park173 to form the isolation structures in the peripheral region and the memory region to have different depths and widths to arrive at the claimed invention. One would have been motivated by the teachings of Park173 to improve the integration of the device using this method.
Regarding claim 20: Claim 20 is rejected in the same manner as claim 19.
Citation of pertinent prior art
Lee et al. (US 20070272971 A1) teaches a method for making a memory device including forming the first isolation structure in the peripheral region before forming the second isolation structure in the memory region, the first and second isolation structures having different widths and heights, and a control gate layer being deposited over the peripheral and memory regions.
Conclusion
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/ROBERT L STEWART/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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