DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election claims 17-20 and the addition of claims 21-36 in the reply filed on 07/17/26 is acknowledged. Claims 1-16 have been canceled by Applicants.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 02/12/25 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 17-20 and 31-36 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2022/0223565).
a. Re claim 17, Chen et al. disclose a method of forming an interposer, comprising: forming a molding material 127 around a semiconductor die 204 (see figs. 1A-J&10-11 and related text as well as [0024] and remaining of disclosure for more details) such that the molding material laterally surrounds the semiconductor die, wherein the molding material is formed such that a side of the semiconductor die, comprising a first electrical contact 209 (leftmost) formed in a semiconductor substrate, is exposed (see fig. 1c); performing a recess etch process on the semiconductor substrate to remove a portion of the semiconductor substrate such that a first protruding portion of the first electrical contact is protruding from a surface 205c (figs. 1D-E, [0037]) of the semiconductor substrate; depositing a dielectric material 130 (fig. 1F, [0040]) over the surface of the semiconductor substrate and the first electrical contact; and performing a planarization process (fig. 1G and related text) to remove a portion of the dielectric material to expose a first contact surface of the first electrical contact (explicit on fig. 1G) and to thereby form a dielectric isolation layer 130A ([0043]) that is located between the surface of the semiconductor substrate and a plane parallel to the first contact surface of the first electrical contact, such that the dielectric isolation layer laterally surrounds the first protruding portion of the first electrical contact but does not cover the first contact surface of the first electrical contact (explicit on fig. 1G).
b. Re claim 18, the method of claim 17, further comprises forming a redistribution layer by performing operations comprising: forming a polymer layer 137 (fig. 1H and related text) over the semiconductor die and the molding material such that the polymer layer is at least partially covering the dielectric isolation layer; forming at least one redistribution interconnect 141 (fig. 1I and related text) in the polymer layer; and forming a first redistribution via 139 in the polymer layer such that the first redistribution via forms an electrical connection between the first contact surface of the first electrical contact and the at least one redistribution interconnect (in the alternative to the above, the polymer can be layer 133 on figs. 10-11, the first redistribution via 135, and the redistribution interconnect 143).
c. Re claim 19, the method of claim 18, further comprises forming the dielectric isolation layer to laterally extend beyond the first contact surface such that any misalignment between the first redistribution via and the first contact surface only causes the first redistribution via to partially contact the first contact surface of the first electrical contact and to partially contact the dielectric isolation layer (explicit on fig. 1I&10-11), but not to contact the semiconductor substrate, such that the dielectric isolation layer prevents an electrically conducting pathway from forming between the first redistribution via and the semiconductor substrate (explicit on fig. 1I&10-11).
d. Re claim 20, the semiconductor die further comprises a second electrical contact 209 (next to the right side of the first one as defined above) comprising a second protruding portion that protrudes from the surface of the semiconductor substrate (explicit on figs. 1E-J&10-11), the method further comprising: forming the dielectric isolation layer to be located between the surface of the semiconductor substrate and a plane parallel to a second contact surface of the second electrical contact such that the dielectric isolation layer laterally surrounds the second protruding portion of the second electrical contact but does not cover the second contact surface of the second electrical contact (explicit on figs. 1E-J&10-11).
e. Re claim 31, Chen et al. disclose a method of forming an interposer, comprising: forming a molding material 127 around a semiconductor die 204 such that the molding material laterally surrounds the semiconductor die (see figs. 1A-J&4A-11 and related text as well as [0024] and remaining of disclosure for more details), wherein the semiconductor die comprises a first electrical contact 209 (leftmost) and a second electrical contact 209 (next to first one on the right) formed in a semiconductor substrate 205; performing a recess etch process on the semiconductor substrate to remove a portion of the semiconductor substrate such that a first protruding portion of the first electrical contact and a second protruding portion of the second electrical contact each protrude from a surface 205c of the semiconductor substrate (figs. 1D-E, [0037]); depositing a dielectric material 130 (fig. 1F; or 130’1&130’2 on figs. 4A-5C and related text) over the surface of the semiconductor substrate, the first electrical contact, and the second electrical contact; and performing a planarization process to remove a portion of the dielectric material to expose a first contact surface of the first electrical contact and a second contact surface of the second electrical contact and to thereby form a dielectric isolation layer 130A that laterally surrounds the first protruding portion and the second protruding portion but does not cover the first contact surface or the second contact surface (fig. 1G).
f. Re claim 32, the dielectric isolation layer comprises (i.e. is) a single portion that laterally surrounds both the first protruding portion of the first electrical contact and the second protruding portion of the second electrical contact (explicit on fig. 1G).
g. Re claim 33, the dielectric isolation layer comprises a first portion 130D (figs. 6A-G and related text) that laterally surrounds the first protruding portion of the first electrical contact and a second portion 130D that laterally surrounds the second protruding portion of the second electrical contact, such that the first portion and the second portion are disconnected from one another.
h. Re claim 34, the semiconductor die further comprises a third electrical contact comprising (one of the contact 209 surrounded by the leftmost portion 130D on fig. 6C, noting that another one of the contacts 209 surrounded by that leftmost portion 130D would be the first contact 209 defined in claim 31 rejection above) a third protruding portion and a fourth electrical contact (one of the contact 209 surrounded by the portion 130D on the right of the leftmost portion of 130D on fig. 6C, noting that another one of the contacts 209 surrounded by that portion 130D on the right of the leftmost portion of 130D would be the second contact 209 defined in claim 31 rejection above) comprising a fourth protruding portion that each protrude from the surface of the semiconductor substrate (explicit in view of figs. 6A&6C), wherein the first portion of the dielectric isolation layer laterally surrounds the first protruding portion of the first electrical contact and the third protruding portion of the third electrical contact (explicit in view of figs. 6A&6C), and wherein the second portion of the dielectric isolation layer laterally surrounds the second protruding portion of the second electrical contact and the fourth protruding portion of the fourth electrical contact (explicit in view of figs. 6A&6C).
i. Re claim 35, the dielectric material comprises a polymer, wherein the polymer is polyimide([0042]), benzocyclobutene, or polybenzo-bisoxazole.
j. Re claim 36, the dielectric material (when it is 130’1&130’2 on figs. 4A-5C) comprises a conformal insulating layer 130’1 of silicon nitride ([0059]) or silicon carbide deposited by a chemical vapor deposition process ([0042]).
Claim(s) 21, 23-25, 27-28 and 30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2021/0193582).
a. Re claim 21, Yu et al. disclose a method of forming an interposer, comprising: forming a plurality of through-interposer-vias (TIVs) 220 over a carrier substrate 202 (see fig. 10 and related text; see remaining of disclosure for more details) by: forming a seed layer ([0048]) over the carrier substrate; forming a patterned photoresist over the seed layer ([0048]), the patterned photoresist comprising openings ([0048]); electroplating a metallic fill material into the openings of the patterned photoresist to form the TIVs ([0048]); attaching a semiconductor die 140 (or 100; [0029]) to the carrier substrate; and forming a molding material 222 (fig. 11, [0050]) around the semiconductor die and the TIVs such that the molding material laterally surrounds the semiconductor die and the TIVs.
b. Re claim 23, the metallic fill material comprises copper, nickel, or copper and nickel ([0048]).
c. Re claim 24, the method of claim 21 further comprises, after electroplating the metallic fill material, removing the patterned photoresist by ashing or dissolution in a solvent ([0048]), and etching portions of the seed layer in regions between the electroplated metallic fill material to form the TIVs as separated structures on the carrier substrate ([0048]).
d. Re claim 25, attaching the semiconductor die to the carrier substrate comprises attaching (directly or indirectly) the semiconductor die using an adhesive layer 168 ([0039]).
e. Re claim 27, the method of claim 21, further comprises performing a planarization process to remove portions of the molding material that overlie a horizontal plane including a top surface of the semiconductor die (see figs. 12-13 and related text).
f. Re claim 28, the method of claim 21, further comprises: performing a recess etch process on a semiconductor substrate of the semiconductor die to remove a portion of the semiconductor substrate such that a first protruding portion of a first electrical contact 154 formed in the semiconductor substrate protrudes from a surface of the semiconductor substrate (see fig. 14, [0054]); depositing a dielectric material (dielectric material to form dielectric layer 224; see [0054]) over the surface of the semiconductor substrate and the first electrical contact; and performing a planarization process to remove a portion of the dielectric material to expose a first contact surface of the first electrical contact and to thereby form a dielectric isolation layer 224 that laterally surrounds the first protruding portion of the first electrical contact but does not cover the first contact surface of the first electrical contact (fig. 14, [0054]).
g. Re claim 30, the method of claim 28, further comprises forming a redistribution layer 240 (fig. 15, [0055]-[0062]) by: forming a polymer layer 242&246 ([0056]-[0058]) over the semiconductor die and the molding material such that the polymer layer is at least partially covering the dielectric isolation layer; forming at least one redistribution interconnect 248 in the polymer layer; and forming a first redistribution via (vi portion of 244) in the polymer layer that forms an electrical connection between the first contact surface of the first electrical contact and the at least one redistribution interconnect (explicit on fig. 15).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 22, 26 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2021/0193582).
a. Re claim 22, Yu et al. disclose all the limitations of claim 21 as stated above including wherein forming the seed layer comprises sputtering a stack of a titanium barrier layer and a copper seed layer (see [0048]), except explicitly that the titanium barrier layer has a thickness in a range from 50 nm to 400 nm and the copper seed layer has a thickness in a range from 100 nm to 500 nm. However, it would have been obvious to one skilled in the art (who, according to MPEP 2141.03, is not an automaton but is a person of ordinary creativity who would, of necessity have the capability of understanding the scientific and engineering principles applicable to the pertinent art) to have provided the titanium barrier layer having a thickness in a range from 50 nm to 400 nm and the copper seed layer having a thickness in a range from 100 nm to 500 nm as forming those kind of layers in a seed layer involves typically (in the art) forming them from a few tens of nanometers to a few hundred nanometers, and a skilled in the art would not have found the claimed range to be inventive or involving anything contrary to the understandings and expectations of the art.
b. Re claim 26, Yu et al. disclose all the limitations of claim 21 as stated above including that the molding material comprises an epoxy molding compound that is cured (see [0050]), except explicitly for the molding material having a Young's modulus greater than 3.5 GPa, and wherein forming the molding material comprises curing the epoxy molding compound at a temperature in a range from 125 °C to 150 °C. However, it would have been obvious to one skilled in the art (who, according to MPEP 2141.03, is not an automaton but is a person of ordinary creativity who would, of necessity have the capability of understanding the scientific and engineering principles applicable to the pertinent art) to have provided the molding material having a Young's modulus greater than 3.5 GPa, and wherein forming the molding material comprises curing the epoxy molding compound at a temperature in a range from 125 °C to 150 °C in order to ensure required/desired mechanical performance for the molding material and saving in thermal budget by using a low curing temperature (see MPEP 2144.I&II).
c. Re claim 29, Yu et al. disclose all the limitations of claim 28 as stated above except explicitly that performing the recess etch process comprises forming a patterned photoresist as an etch mask and performing a dry etch using plasma etchant gases or performing a wet etch. However, it would have been obvious to one skilled in the art (who, according to MPEP 2141.03, is not an automaton but is a person of ordinary creativity who would, of necessity have the capability of understanding the scientific and engineering principles applicable to the pertinent art) to have performed the recess etch process to comprise forming a patterned photoresist as an etch mask and performing a dry etch using plasma etchant gases or performing a wet etch, since those steps are standard patterned etching process in the art a skilled in the art would not have found to be inventive or involving anything contrary to the understandings and expectations of the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
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/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899
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