Prosecution Insights
Last updated: October 02, 2026
Application No. 18/613,430

DISPLAY DEVICE

Non-Final OA §103
Filed
Mar 22, 2024
Priority
Mar 24, 2023 — RE 10-2023-0039043 +1 more
Examiner
LUKE, DANIEL M
Art Unit
Tech Center
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
71%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
507 granted / 710 resolved
+11.4% vs TC avg
Strong +19% interview lift
Without
With
+18.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
23 currently pending
Career history
729
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
49.9%
+9.9% vs TC avg
§102
25.8%
-14.2% vs TC avg
§112
21.8%
-18.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 710 resolved cases

Office Action

§103
DETAILED ACTION This office action is in response to the election filed 7/8/2026. Currently, claims 1-20 are pending. Claim 12 has been withdrawn from consideration. Election/Restrictions Applicant’s election without traverse of Species I is acknowledged. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: CAPACITOR STRUCTURE FOR A DISPLAY DEVICE. Furthermore, the disclosure is objected to because of the following informalities: In line 2 of para. [00126], it appears that the term “upper electrode” preceding “CE2a” is erroneous, and should instead by “lower layer”. Appropriate correction is required. Claim Objections Claim 15 is objected to because of the following informalities: In line 8, the word “electrode” is missing following “capacitor”. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 6, 8-11, 15-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Noh et al. (US 2023/0081823). Pertaining to claim 1, Noh shows, with reference to either one of FIG. 12 or 13, a display device comprising: a transistor (TFT) including a semiconductor layer (130) and a gate electrode (150) overlapping a channel area (130n) of the semiconductor layer; and a storage capacitor (Cap) electrically connected to the transistor, the storage capacitor comprising: a first capacitor electrode (CE3) disposed below the semiconductor layer; a second capacitor electrode (CE1) disposed on the first capacitor electrode; and a third capacitor electrode (CE2) disposed on the second capacitor electrode, wherein the second capacitor electrode comprises: a lower layer (231 in FIG. 12, 230 in FIG. 13), the lower layer and the semiconductor layer being disposed on a same layer (120); an intermediate layer (232 in FIG. 12, 241 in FIG. 13) disposed on the lower layer; and an upper layer (240 in FIG. 12, 242 in FIG. 13) disposed on the intermediate layer, and the upper layer of the second capacitor electrode comprises a conductive oxide (para. [0100], [0130]). Pertaining to claim 15, Noh shows, with reference to either one of FIG. 12 or 13, a display device comprising: a transistor (TFT) including a semiconductor layer (130) and a gate electrode (150) overlapping a channel area (130n) of the semiconductor layer; and a storage capacitor (Cap) electrically connected to the transistor and comprising: a first capacitor electrode (CE3) disposed below the semiconductor layer; a second capacitor electrode (CE1) disposed on the first capacitor electrode; and a third capacitor electrode (CE2) disposed on the second capacitor electrode, wherein the second capacitor electrode comprises: a lower layer (231 in FIG. 12, 230 in FIG. 13), the lower layer and the semiconductor layer being disposed on a same layer (120); and an upper layer (either one of 232 or 240 in FIG. 12, or one of 241 or 242 in FIG. 13) disposed on the lower layer, and each of the lower layer and the upper layer of the second capacitor electrode comprises a conductive oxide (para. [0091], [0100], [0130]). Although Noh does not explicitly show the conductive oxide to be amorphous, this is one of a limited number of possibilities for the crystalline structure of the conductive oxide material. Thus, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to try a conductive oxide material having an amorphous structure for the conductive oxide material of Noh, as the court has held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is prima facie obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Pertaining to claim 2, Noh shows a buffer layer (120) disposed between the first capacitor electrode and the second capacitor electrode; and an inorganic insulating layer (140) comprising a first insulating pattern (left portion) disposed between the semiconductor layer and the gate electrode and a second insulating pattern (right portion) disposed between the second capacitor electrode and the third capacitor electrode, wherein the first insulating pattern is disposed directly on the semiconductor layer and the second insulating pattern is disposed directly on the upper layer of the second capacitor electrode. Pertaining to claim 6, although Noh does not explicitly show the conductive oxides to be amorphous, this is one of a limited number of possibilities for the crystalline structure of the conductive oxide material. Thus, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to try a conductive oxide material having an amorphous structure for the conductive oxide material layers of Noh, as the court has held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is prima facie obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Pertaining to claims 8-10, Noh shows the intermediate and lower layers in FIG. 12 may comprise IGZO (para. [0083]) having different relative compositions (para. [0177]). Although Noh does not explicitly show the relative compositions of the indium and gallium being in a range of 10-30 and 0-20 at%, respectively, it would have been obvious to one having ordinary skill in the art, before the effective filing date of the pending application, for the relative compositions to fall within these claimed ranges, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955). Although Noh does not explicitly show the IGZO material to be amorphous, this is one of a limited number of possibilities for the crystalline structure of the IGZO material. Thus, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to try a IGZO material having an amorphous structure for the IGZO material of Noh, as the court has held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is prima facie obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Pertaining to claim 11, Noh shows the intermediate layer is disposed in an entire area between the lower layer and the upper layer of the second capacitor electrode (FIG. 12, 13). Pertaining to claim 16, Noh shows the upper layer comprises ZIO (para. [0083]). Pertaining to claim 18, Noh shows the second capacitor electrode further comprises an intermediate layer (232 or 241) disposed between the lower layer and the upper layer of the second capacitor electrode, and the intermediate layer comprises an amorphous conductive oxide including atoms included in the lower layer and atoms included in the upper layer of the second capacitor electrode (all layers may include oxygen, for example – para. [0083], [0095], [0128], [0130]). Claims 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Noh as applied to claims 1 and 15 above, and further in view of Lee et al. (US 2023/0137236). Noh teaches the display device of claims 1 and 15, but fails to teach the wiring and conductive layer. However, Lee teaches in FIG. 5A that, in a display device similar to Noh, a wiring WL1 is disposed on a same layer as the first capacitor electrode CE1, and a conductive layer M1 is disposed on the semiconductor layer ACT and electrically connected to the wiring, and the conductive layer and the upper layer M3 of the second capacitor electrode are disposed on a same layer. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to apply Lee’s teaching of the wiring and conductive layer to the display device of Noh, with the motivation that the wiring and conductive layer act to provide power or data to the transistor (para. [0100]). Allowable Subject Matter Claims 3-5, 7, 14, 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Pertaining to claims 3-5 and 19, neither Noh nor any of the other prior art of record teaches or suggests a thickness of the intermediate layer is less than a thickness of the upper layer and a thickness of the lower layer of the second capacitor electrode. Pertaining to claims 7 and 17, neither Noh nor any of the other prior art of record teaches or suggests the particular ZIO compositions as claimed. Pertaining to claim 14, the prior art of record, particularly Lee, fails to teach or suggest the conductive layer comprises a first conductive layer disposed on a same layer as the intermediate layer of the second capacitor electrode, and a second conductive layer disposed on the first conductive layer and being disposed on a same layer as the upper layer of the second capacitor electrode. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yoon et al. (US 2023/0070323), Choi et al. (US 2023/0131822), and Liu (US 12,598,866) all teach display devices having transistor and capacitor structures similar to those of Applicant’s invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL LUKE/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Mar 22, 2024
Application Filed
Aug 24, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751313
SELECTIVE ALTERATION OF INTERCONNECT PADS FOR DIRECT BONDING
5y 7m to grant Granted Sep 29, 2026
Patent 12751223
Treatment to Control Deposition Rate
4y 4m to grant Granted Sep 29, 2026
Patent 12745616
SEMICONDUCTOR STRUCTURE INCLUDING LINES OF DIFFERENT HEIGHT
3y 1m to grant Granted Sep 22, 2026
Patent 12740097
STRUCTURE WITH ISOLATED WELL
3y 7m to grant Granted Sep 15, 2026
Patent 12740397
SEMICONDUCTOR PATTERN AND METHOD OF ROUNDING THE SAME
3y 6m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
71%
Grant Probability
90%
With Interview (+18.6%)
2y 9m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 710 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month