DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Colombeau et al. (US Publication No. 2023/0040606) in view of Murakoshi et al. (US Publication No. 2017/0263613).
Regarding claim 1, Colombeau discloses a semiconductor device comprising:
a substrate (102)
a plurality of spaced apart gate stacks (106) on the substrate defining respective trenches (114) therebetween, each gate stack comprising alternating layers of first (108) and second semiconductor materials (110), the layers of the second semiconductor material defining nanostructures (paragraph 43)
respective source/drain regions (120/122) within the trenches
respective insulating regions (112) adjacent lateral ends of the layers of the first semiconductor material (108)
While Colombeau does disclose a super lattice structure (106), Colombeau does not disclose respective dopant blocking superlattices adjacent lateral ends of the nanostructures and offset outwardly from adjacent surfaces of the insulating regions, each dopant blocking superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. However, Murakoshi discloses respective dopant blocking superlattices adjacent lateral ends of the nanostructures (6b) and offset outwardly from adjacent surfaces of the insulating regions (23), each dopant blocking superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers (16/17) defining a base semiconductor portion, and at least one non-semiconductor monolayer (15) constrained within a crystal lattice of adjacent base semiconductor portions (16/17) (Figure 16B). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the device of Colombeau to include respective dopant blocking superlattice layering adjacent to lateral ends of the nanostructures, as taught by Murakoshi, since it can provide improved electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage (paragraph 4).
Regarding claim 2, Murakoshi discloses a respective semiconductor buffer layer (25) between each nanostructure (6b) and the adjacent dopant blocking superlattice (15/16/17). As explained above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Colombeau in view of Murakoshi.
Regarding claim 3, Murakoshi discloses a respective lateral bottom dopant blocking superlattice between the substrate and the source/drain regions (Figures 133B and 135), each lateral bottom dopant blocking superlattice comprising a plurality of stacked groups of layers (the lower most blocking pattern is between the substrate and part of the S/D region), each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion (16/17), and at least one non-semiconductor monolayer (15) constrained within a crystal lattice of adjacent base semiconductor portions (16/17).
Regarding claim 4, Colombeau discloses the first semiconductor material (106) comprises silicon germanium (paragraph 43).
Regarding claim 5, Colombeau discloses the second semiconductor material (108) comprises silicon (paragraph 43).
Regarding claim 6, Colombeau discloses the source/drain regions (120/122) comprise phosphorus doped silicon (Si:P) (paragraph 54).
Regarding claim 7, Murakoshi discloses the base semiconductor monolayers (17) comprise silicon (HfSiON). As explained above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Colombeau in view of Murakoshi.
Regarding claim 8, Murakoshi discloses the non-semiconductor monolayers (25) comprise oxygen (paragraph 163). As explained above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Colombeau in view of Murakoshi.
Regarding claim 9, Colombeau discloses a semiconductor device comprising:
a substrate (102)
a plurality of spaced apart gate stacks (106) on the substrate defining respective trenches (114) therebetween, each gate stack comprising alternating layers of first (108) and second semiconductor materials (110), the layers of the second semiconductor material defining nanostructures (paragraph 43)
respective source/drain regions (120/122) within the trenches
respective insulating regions (112) adjacent lateral ends of the layers of the first semiconductor material (108)
While Colombeau does disclose a super lattice structure (106), Colombeau does not disclose a respective buffer layer between each nanostructure and dopant blocking superlattice, and respective dopant blocking superlattices adjacent lateral ends and a bottom dopant blocking superlattice between the substrate and source/drain regions of the nanostructures and offset outwardly from adjacent surfaces of the insulating regions, each dopant blocking superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. However, Murakoshi discloses a respective buffer layer (25) between each nanostructure (6b) and dopant blocking superlattice (15/16/17) (Figure 16B), and respective dopant blocking superlattices adjacent lateral ends and a bottom dopant blocking superlattice between the substrate and source/drain regions of the nanostructures (6b) and offset outwardly from adjacent surfaces of the insulating regions (23), each dopant blocking superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers (16/17) defining a base silicon portion, and at least one non-semiconductor monolayer (15) constrained within a crystal lattice of adjacent base silicon portions (16/17) (Figure 16B). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the device of Colombeau to include respective dopant blocking superlattice layering adjacent to lateral ends of the nanostructures, as taught by Murakoshi, since it can provide improved electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage (paragraph 4).
Regarding claim 10, Colombeau discloses the first semiconductor material (106) comprises silicon germanium (paragraph 43).
Regarding claim 11, Colombeau discloses the second semiconductor material (108) comprises silicon (paragraph 43).
Regarding claim 12, Colombeau discloses the source/drain regions (120/122) comprise phosphorus doped silicon (Si:P) (paragraph 54).
Regarding claim 13, Murakoshi discloses the base semiconductor monolayers (17) comprise silicon (HfSiON). As explained above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Colombeau in view of Murakoshi.
Regarding claim 14, Murakoshi discloses the non-semiconductor monolayers (25) comprise oxygen (paragraph 163). As explained above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Colombeau in view of Murakoshi.
Regarding claim 15, Colombeau discloses a semiconductor device comprising:
a substrate (102)
a plurality of spaced apart gate stacks (106) on the substrate defining respective trenches (114) therebetween, each gate stack comprising alternating layers of first (108) and second semiconductor materials (110), the layers of the second semiconductor material defining nanostructures (paragraph 43)
respective source/drain regions (120/122) within the trenches
respective insulating regions (112) adjacent lateral ends of the layers of the first semiconductor material (108)
While Colombeau does disclose a super lattice structure (106), Colombeau does not disclose respective dopant blocking superlattices adjacent lateral ends of the nanostructures and offset outwardly from adjacent surfaces of the insulating regions, each dopant blocking superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. However, Murakoshi discloses respective dopant blocking superlattices adjacent lateral ends of the nanostructures (6b) and offset outwardly from adjacent surfaces of the insulating regions (23), each dopant blocking superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers (16/17) defining a base semiconductor portion, and at least one non-semiconductor monolayer (15) constrained within a crystal lattice of adjacent base semiconductor portions (16/17) (Figure 16B). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the device of Colombeau to include respective dopant blocking superlattice layering adjacent to lateral ends of the nanostructures, as taught by Murakoshi, since it can provide improved electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage (paragraph 4).
Regarding claim 16, Murakoshi discloses a respective semiconductor buffer layer (25) between each nanostructure (106) and the adjacent dopant blocking superlattice. As explained above, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified Colombeau in view of Murakoshi.
Regarding claim 17, Murakoshi discloses a respective lateral bottom dopant blocking superlattice between the substrate and the source/drain regions (Figures 133B and 135), each lateral bottom dopant blocking superlattice comprising a plurality of stacked groups of layers (the lower most blocking pattern is between the substrate and part of the S/D region), each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion (16/17), and at least one non-semiconductor monolayer (15) constrained within a crystal lattice of adjacent base semiconductor portions (16/17).
Regarding claim 18, Colombeau discloses the first semiconductor material (106) comprises silicon germanium (paragraph 43).
Regarding claim 19, Colombeau discloses the second semiconductor material (108) comprises silicon (paragraph 43).
Regarding claim 20, Colombeau discloses the source/drain regions (120/122) comprise phosphorus doped silicon (Si:P) (paragraph 54).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Morooka (US Publication No. 2023/0200060) discloses dopant blocking superlattice structures (SST) adjacent to nanostructure (Figure 4). Rubin discloses nanosheet blocking layers (270) adjacent to a nanostructure (Figure 5). More et al. (US Publication No. 2023/0012054) discloses boron doped silicon regions (218) adjacent to silicon layers (Figure 2E).
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/N.R.P/ 6/20/2026 Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
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