DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 08/19/2026 has been entered. Claims 1, 5-14 and 17-19 remain pending in the application. Claims 2-4, 15 and 16 have been cancelled.
Drawings
The Amendments of the specification made on 08/19/2026, in paragraph [0050], result in Fig.5G no longer being required.
Replacement drawings corresponding to figures 4C, 4D, 5C, 5D, 7E and 7F were received on 08/19/2026. These drawings are acceptable except for the drawing corresponding to Fig.5D.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because in Fig.5D reference character “ 125b’ ” has been used to designate both the superlattice on the cap layer 106 a and the superlattice on the cap layer 106b,
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/06/2026 and 08/18/2026 have been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 9 and 17 recite the limitation “the conductive contact liner”. There is insufficient antecedent basis for this limitation, and it is not clear which conductive contact liner out of the respective conductive contact liners is the limitation referring too. For the purpose of examination, the claim limitation will be interpreted as “a conductive contact liner”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 6, 8-11, 13-14, 17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al., (United States Patent Application Number, US 2022/0359208 A1), hereinafter referenced Lin.
Regarding claim 1, Lin teaches a semiconductor device comprising: a substrate (Fig.4, elements #218); a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween (Fig.4, formed by elements #312, #414, #348, #320, #220, #212, #222, #224), each gate stack comprising alternating layers of first and second semiconductor materials (Fig.4, layers #212 correspond to the first semiconductor material, silicon germanium, paragraph [0023], rows 3-4, and layers #220, #222 and #224 correspond to second semiconductor material, silicon, paragraph [0022], rows 12-16, paragraph [0023], rows 1-2), the layers of the second semiconductor material defining nanostructures (paragraph [0022], rows 1-2); respective source/drain regions within the trenches (Fig.2, elements #202 and #204); respective insulating regions adjacent lateral ends of the layers of the first semiconductor material (Fig.4, element #226, paragraph [0020], rows 9-13); and respective conductive contact liners in the trenches (Fig.4, elements #408, paragraph [0031], rows 3-4), with surface of the nanostructures being offset inwardly from adjacent surface of the insulating regions (Fig.4, lateral surfaces of elements #220, #222 and #224 are offset inwardly from adjacent surface of elements #226).
Regarding claim 5, Lin teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Lin further teaches the semiconductor device of claim 1 wherein the first semiconductor material comprises silicon germanium (paragraph [0023], rows 3-4).
Regarding claim 6, Lin teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Lin further teaches the semiconductor device of claim 1 wherein the second semiconductor material comprises silicon (paragraph [0023], rows 1-2).
Regarding claim 8, Lin teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Lin further teaches the semiconductor device of claim 1 wherein the conductive contact liners comprise silicide (paragraph [0031], rows 3-4).
Regarding claim 9, Lin teaches a semiconductor device comprising: a substrate (Fig.4, elements #218); a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween (Fig.4, formed by elements #312, #414, #348, #320, #220, #212, #222, #224), each gate stack comprising alternating layers of first and second semiconductor materials (Fig.4, layers #212 correspond to the first semiconductor material, silicon germanium, paragraph [0023], rows 3-4, and layers #220, #222 and #224 correspond to second semiconductor material, silicon, paragraph [0022], rows 12-16, paragraph [0023], rows 1-2), the layers of the second semiconductor material defining nanostructures (paragraph [0022], rows 1-2); respective source/drain regions within the trenches (Fig.2, elements #202 and #204); respective insulating regions adjacent lateral ends of the layers of the first semiconductor material (Fig.4, element #226, paragraph [0020], rows 9-13), with surfaces of the nanostructures being offset inwardly from adjacent surfaces of the insulating regions (Fig.4, lateral surfaces of elements #220, #222 and #224 are offset inwardly from adjacent surface of elements #226); respective conductive contact liners in the trenches (Fig.4, elements #408, paragraph [0031], rows 3-4); and a respective metal plug in each trench adjacent a conductive contact liner (Fig.4, element #310).
Regarding claim 10, Lin teaches the semiconductor device of claim 9 as set forth in the anticipation rejection. Lin further teaches the semiconductor device of claim 9 wherein the first semiconductor material comprises silicon germanium (paragraph [0023], rows 3-4).
Regarding claim 11, Lin teaches the semiconductor device of claim 9 as set forth in the anticipation rejection. Lin further teaches the semiconductor device of claim 9 wherein the second semiconductor material comprises silicon (paragraph [0023], rows 1-2).
Regarding claim 13, Lin teaches the semiconductor device of claim 9 as set forth in the anticipation rejection. Lin further teaches the semiconductor device of claim 9 wherein the conductive contact liners comprise silicide (paragraph [0031], rows 3-4).
Regarding claim 14, Lin teaches a semiconductor device comprising: a substrate (Fig.4, elements #218); a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween (Fig.4, formed by elements #312, #414, #348, #320, #220, #212, #222, #224), each gate stack comprising alternating layers of silicon and silicon germanium, (Fig.4, layers #212 are silicon germanium layers, paragraph [0023], rows 3-4, and layers #220, #222 and #224 are silicon layers, paragraph [0022], rows 12-16, paragraph [0023], rows 1-2), the silicon layers of defining nanostructures (paragraph [0022], rows 1-2); respective source/drain regions within the trenches (Fig.2, elements #202 and #204); respective insulating regions adjacent lateral ends of the silicon germanium layers (Fig.4, element #226, paragraph [0020], rows 9-13); and respective conductive contact liners in the trenches (Fig.4, elements #408, paragraph [0031], rows 3-4) with surfaces of the nanostructures being offset inwardly from adjacent surfaces of the insulating regions (Fig.4, lateral surfaces of elements #220, #222 and #224 are offset inwardly from adjacent surface of elements #226).
Regarding claim 17, Lin teaches the semiconductor device of claim 14 as set forth in the anticipation rejection. Lin further teaches the semiconductor device of claim 14 further comprises a respective metal plug in each trench adjacent a conductive contact liner (Fig.4, element #310).
Regarding claim 19, Lin teaches the semiconductor device of claim 14 as set forth in the anticipation rejection. Lin further teaches the semiconductor device of claim 14 wherein the conductive contact liners comprise silicide (paragraph [0031], rows 3-4).
Claims 1, 7, 9, 12, 14 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang, (United States Patent Application Number, US 2021/0305393 A1), hereinafter referenced Wang.
Regarding claim 1, Wang teaches a semiconductor device comprising: a substrate (Fig.12, elements #202); a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween (Fig.12, formed by elements #216, #226, #238, #206, #206, elements #206 are labeled in Fig.4), each gate stack comprising alternating layers of first and second semiconductor materials (Fig.4, layers #206 correspond to the first semiconductor material, silicon germanium, paragraph [0015], rows 41-42, and layers #208 correspond to second semiconductor material, silicon, paragraph [0015], rows 42-44), the layers of the second semiconductor material defining nanostructures (paragraph [0016], rows 24-25, paragraph [0002], rows 11-16); respective source/drain regions within the trenches (Fig.12, elements #205SD); respective insulating regions adjacent lateral ends of the layers of the first semiconductor material (Fig.12, element #220, paragraph [0023], rows 23-27); and respective conductive contact liners in the trenches (Fig.12, elements #234, paragraph [0032], rows 1-3), with surface of the nanostructures being offset inwardly from adjacent surface of the insulating regions (Fig.12, outer lateral surfaces of elements #208 are offset inwardly from adjacent outer lateral surfaces of elements #220).
Regarding claim 7, Wang teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Wang further teaches the semiconductor device of claim 1 wherein the source/drain regions comprise phosphorus doped silicon (Si:P) (Fig.12, element #230, paragraph [0031], rows 3-4).
Regarding claim 9, Wang teaches a semiconductor device comprising: a substrate (Fig.12, elements #202); a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween (Fig.12, formed by elements #216, #226, #238, #206, #206, elements #206 are labeled in Fig.4), each gate stack comprising alternating layers of first and second semiconductor materials (Fig.4, layers #206 correspond to the first semiconductor material, silicon germanium, paragraph [0015], rows 41-42, and layers #208 correspond to second semiconductor material, silicon, paragraph [0015], rows 42-44), the layers of the second semiconductor material defining nanostructures (paragraph [0016], rows 24-25, paragraph [0002], rows 11-16); respective source/drain regions within the trenches (Fig.12, elements #205SD); respective insulating regions adjacent lateral ends of the layers of the first semiconductor material (Fig.12, element #220, paragraph [0023], rows 23-27), with surfaces of the nanostructures being offset inwardly from adjacent surfaces of the insulating regions (Fig.12, outer lateral surfaces of elements #208 are offset inwardly from adjacent outer lateral surfaces of elements #220); respective conductive contact liners in the trenches (Fig.12, elements #234, paragraph [0032], rows 1-3); and a respective metal plug in each trench adjacent the conductive contact liner (Fig.12, element #236, paragraph [0033], rows 1-2).
Regarding claim 12, Wang teaches the semiconductor device of claim 9 as set forth in the anticipation rejection. Wang further teaches the semiconductor device of claim 9 wherein the source/drain regions comprise phosphorus doped silicon (Si:P) (Fig.12, element #230, paragraph [0031], rows 3-4).
Regarding claim 14, Wang teaches a semiconductor device comprising: a substrate (Fig.12, elements #202); a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween (Fig.12, formed by elements #216, #226, #238, #206, #206, elements #206 are labeled in Fig.4), each gate stack comprising alternating layers of silicon and silicon germanium (Fig.4, layers #206 comprise silicon germanium, paragraph [0015], rows 41-42, and layers #208 comprise silicon, paragraph [0015], rows 42-44), the layers of the silicon layers defining nanostructures (paragraph [0016], rows 24-25, paragraph [0002], rows 11-16); respective source/drain regions within the trenches (Fig.12, elements #205SD); respective insulating regions adjacent lateral ends of the silicon germanium layers (Fig.12, element #220, paragraph [0023], rows 23-27), and respective conductive contact liners in the trenches (Fig.12, elements #234, paragraph [0032], rows 1-3), with surfaces of the nanostructures being offset inwardly from adjacent surfaces of the insulating regions (Fig.12, outer lateral surfaces of elements #208 are offset inwardly from adjacent outer lateral surfaces of elements #220).
Regarding claim 18, Wang teaches the semiconductor device of claim 14 as set forth in the anticipation rejection. Wang further teaches the semiconductor device of claim 14 wherein the source/drain regions comprise phosphorus doped silicon (Si:P) (Fig.12, element #230, paragraph [0031], rows 3-4).
Response to Arguments
Applicant’s arguments filed on 08/19/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
