DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The subject matter of this application admits of illustration by a drawing to facilitate understanding of the invention. Applicant is required to furnish a drawing under 37 CFR 1.81(c). No new matter may be introduced in the required drawing. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d).
Paragraph [0050] of the specification refers to Fig.5G and element #121’. Figure 5G has not been provided.
The drawings are objected to under 37 CFR 1.83(a) because they fail to show element 120’ as described in the specification in paragraph [0050]. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 15-19 are objected to under 37 CFR 1.75 as being a substantial duplicate of claims 2, 3, 4, 7 and 8 respectively. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
For the purpose of examination, claims 15-19 will be interpreted as being dependent on claim 14.
Claim 14 is objected to because of the following informalities: “silicon layers of defining nanostructures” should read “silicon layers defining nanostructures”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-8, 14 and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rubin et al., (United States Patent Number, US 10,748,901 B2), hereinafter referenced as Rubin.
Regarding claim 1, a semiconductor device comprising: a substrate (Fig.6, element #100); a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween (Fig.6, formed by elements #DG1, #DG2, #N1-N5 and #206), each gate stack comprising alternating layers of first and second semiconductor materials (Fig.6, first semiconductor layers, elements #N1, #N3 and #N5 alternate with second semiconductor layers, elements #N2 and #N4), the layers of the second semiconductor material defining nanostructures (Fig.6, elements #N2 and #N4 are nanosheets, column 6, rows 1-2); respective source/drain regions within the trenches (Fig.5, elements #R1, #R2 and #R3, column 10, rows 20-21); respective insulating regions adjacent lateral ends of the layers of the first semiconductor material (Fig.6, elements #260, column 12, rows 43-45); and respective conductive contact liners in the trenches (Fig.6, elements #275).
Regarding claim 3, Rubin teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Rubin further teaches the semiconductor device of claim 1 wherein surfaces of the nanostructures are flush with adjacent surfaces of the insulating regions (Fig.6, right and left surfaces of elements #N2 and #N4 are flush with adjacent outer left and right surfaces of elements #260).
Regarding claim 4, Rubin teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Rubin further teaches the semiconductor device of claim 1 further comprising a respective metal plug in each trench adjacent the conductive contact liner (Fig.6, elements #280 and #290, column 15, rows 13-15).
Regarding claim 5, Rubin teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Rubin further teaches the semiconductor device of claim 1 wherein the first semiconductor material comprises silicon germanium (column 9, rows 60-64).
Regarding claim 6, Rubin teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Rubin further teaches the semiconductor device of claim 1 wherein the second semiconductor material comprises silicon (column 9, rows 59-60).
Regarding claim 7, Rubin teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Rubin further teaches the semiconductor device of claim 1 wherein the source/drain regions comprise phosphorus doped silicon (Si:P) (elements #270, column 1, rows 53-64, may be phosphorus doped silicon, column 13, rows 30-36).
Regarding claim 8, Rubin teaches the semiconductor device of claim 1 as set forth in the anticipation rejection. Rubin further teaches the semiconductor device of claim 1 wherein the conductive contact liners comprise silicide (elements #275, column 14, rows 53).
Regarding claim 14, Rubin teaches a semiconductor device comprising: a substrate (Fig.6, element #100); a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween (Fig.6, formed by elements #DG1, #DG2, #N1-N5 and #206), each gate stack comprising alternating layers of silicon and silicon germanium (Fig.6, first semiconductor layers, elements #N1, #N3 and #N5 are silicon germanium layers, alternating with second semiconductor layers, elements #N2 and #N4, which are silicon layers, column 9, rows 59-64), the silicon layers
Regarding claim 16, Rubin teaches the semiconductor device of claim 14 as set forth in the anticipation rejection. Rubin further teaches the semiconductor device of claim 14 wherein surfaces of the nanostructures are flush with adjacent surfaces of the insulating regions (Fig.6, right and left surfaces of elements #N2 and #N4 are flush with adjacent surfaces of elements #260).
Regarding claim 17, Rubin teaches the semiconductor device of claim 14 as set forth in the anticipation rejection. Rubin further teaches the semiconductor device of claim 14 further comprising a respective metal plug in each trench adjacent the conductive contact liner (Fig.6, elements #280 and #290, column 15, rows 13-15).
Regarding claim 18, Rubin teaches the semiconductor device of claim 14 as set forth in the anticipation rejection. Rubin further teaches the semiconductor device of claim 14 wherein the source/drain regions comprise phosphorus doped silicon (Si:P) (elements #270, column 1, rows 53-64, may be phosphorus doped silicon, column 13, rows 30-36).
Regarding claim 19, Rubin teaches the semiconductor device of claim 14 as set forth in the anticipation rejection. Rubin further teaches the semiconductor device of claim 14 wherein the conductive contact liners comprise silicide (elements #275, column 14, rows 53).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 9-11, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hall et al., (United States Patent Application Publication Number, US 2023/0290862 A1) hereinafter referenced as Hall in view of Rubin.
Regarding claim 1, Hall teaches a semiconductor device comprising: a substrate (Fig.7, element #10); a gate stack on the substrate (Fig.7, formed by elements #12-18, #25, #27, #19 and #20) and source/drain regions on each side of the gate stack (Fig.7, elements #28).
Hall does not teach a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween, respective source/drain regions within the trenches. Rubin teaches a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween (Fig.6, gate stacks formed by elements #DG1, #DG2, #N1-N5 and #206, on the substrate #100), respective source/drain regions within the trenches (Fig.5, elements #R1, #R2 and #R3, column 10, rows 20-21). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Rubin and disclose a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween, respective source/drain regions within the trenches. As disclosed by Rubin, this allows simultaneous fabrication of a plurality of semiconductor devices/ transistors that can form an integrated circuit device.
Hall further teaches each gate stack comprising alternating layers of first and second semiconductor materials (Fig.7, first semiconductor material is SiGe and second semiconductor material is Si, Note that all gate stack of Rubin have the same structure), the layers of the second semiconductor material defining nanostructures (second semiconductor material forms nanosheets, paragraph [0043], rows 10-11); source/drain regions (Fig.7, elements #28, which correspond to the location of the trenches taught by Rubin) respective insulating regions adjacent lateral ends of the layers of the first semiconductor material (Fig.7, elements #25, paragraph [0048], rows 5-7); and respective conductive contact liners in the trenches (Fig.7, elements #27).
Regarding claim 2, the combination of Hall and Rubin teaches the semiconductor device of claim 1 as set forth in the obviousness rejection. Hall further teaches the semiconductor device of claim 1 wherein surfaces of the nanostructures are offset inwardly from adjacent surfaces of the insulating regions (Fig.7, left and right surfaces of Si nanostructures are offset inwardly form the outer left and right surfaces of elements #25).
Regarding claim 9, Hall teaches a substrate(Fig.7, element #10); a gate stack on the substrate (Fig.7, formed by elements #12-18, #25 #27, 19 and #20) and source/drain regions on each side of the gate stack (Fig.7 elements #28). Hall does not teach a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween, respective source/drain regions within the trenches. Rubin teaches a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween (Fig.6, gate stacks formed by elements #DG1, #DG2, #N1-N5 and #206, on the substrate #100), respective source/drain regions within the trenches (Fig.5, elements #R1, #R2 and #R3, column 10, rows 20-21). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Rubin and disclose a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween, respective source/drain regions within the trenches. As disclosed by Rubin, this allows simultaneous fabrication of a plurality of semiconductor devices/ transistors that can form an integrated circuit device.
Hall further teaches each gate stack comprising alternating layers of first and second semiconductor materials (Fig.7, first semiconductor material is SiGe and second semiconductor material is Si, Note that all gate stack of Rubin have the same structure), the layers of the second semiconductor material defining nanostructures (second semiconductor material forms nanosheets, paragraph [0043], rows 10-11); respective insulating regions adjacent lateral ends of the layers of the first semiconductor material (Fig.7, elements #25, paragraph [0048], rows 5-7), with surfaces of the nanostructures being offset inwardly from adjacent surfaces of the insulating regions (Fig.7, left and right surfaces of Si nanostructures are offset inwardly form the outer left and right surfaces of elements #25); respective conductive contact liners in the trenches (Fig.7, elements #27), and a respective metal plug in each trench adjacent to the contact liner (Fig.7 shows tungsten plugs).
Regarding claim 10, the combination of Hall and Rubin teaches the semiconductor device of claim 9 as set forth in the obviousness rejection. Hall further teaches the semiconductor device of claim 9 wherein the first semiconductor material comprises silicon germanium (Fig.7, first semiconductor material comprises the SiGe layers).
Regarding claim 11, the combination of Hall and Rubin teaches the semiconductor device of claim 9 as set forth in the obviousness rejection. Hall further teaches the semiconductor device of claim 9 wherein the second semiconductor material comprises silicon (Fig.7, second semiconductor material comprises the Si layers).
Regarding claim 13, the combination of Hall and Rubin teaches the semiconductor device of claim 9 as set forth in the obviousness rejection. Hall further teaches the semiconductor device of claim 9 wherein the conductive contact liners comprise silicide (Fig.7, elements #27 comprise silicide, paragraph [0049], row 4).
Regarding claim 14 Hall teaches a semiconductor device comprising: a substrate (Fig.7, formed by elements #12-18, #25 #27, 19 and #20); a gate stack on the substrate (Fig.7, formed by elements #12-18, #25 #27, 19 and #20) and source/drain regions on each side of the gate stack (Fig.7, elements #28).
Hall does not teach a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween, respective source/drain regions within the trenches. Rubin teaches a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween (Fig.6, gate stacks formed by elements #DG1, #DG2, #N1-N5 and #206, on the substrate #100), respective source/drain regions within the trenches (Fig.5, elements #R1, #R2 and #R3, column 10, rows 20-21). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Rubin and disclose a plurality of spaced apart gate stacks on the substrate with adjacent gate stacks defining a respective trench therebetween, respective source/drain regions within the trenches. As disclosed by Rubin, this allows simultaneous fabrication of a plurality of semiconductor devices/ transistors that can form an integrated circuit device.
Hall further teaches each gate stack comprising alternating layers of silicon and silicon germanium (Fig.7, first semiconductor material is SiGe and second semiconductor material is Si, Note that all gate stack of Rubin have the same structure), the silicon layers of defining nanostructures( silicon forms nanosheets, paragraph [0043], rows 10-11); respective source/drain regions within the trenches (Fig.7, elements #28, which correspond to the trenches of Rubin); respective insulating regions adjacent lateral ends of the silicon germanium layers (Fig.7, elements #25, paragraph [0048], rows 5-7); and respective conductive contact liners in the trenches (Fig.7, elements #27).
Regarding claim 15, the combination of Hall and Rubin teaches the semiconductor device of claim 14 as set forth in the obviousness rejection. Hall further teaches the semiconductor device of claim 14 wherein surfaces of the nanostructures are offset inwardly from adjacent surfaces of the insulating regions (Fig.7, left and right surfaces of Si nanostructures are offset inwardly form the outer left and right surfaces of elements #25).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hall, in view of Rubin and in view of Jambunathan et al., (United States Patent Application Publication Number, US 11,411,096 B2) hereinafter referenced as Jambunathan.
Regarding claim 12, the combination of Hall and Rubin teaches the semiconductor device of claim 9 as set forth in the obviousness rejection. The combination of Hall and Rubin does not teach the semiconductor device of claim 9 wherein the source/drain regions comprise phosphorus doped silicon (Si:P). Jambunathan teaches wherein the source/drain regions comprise phosphorus doped silicon (Si:P) (Fig.7, elements #312 and #314 correspond to elements #112 and #114 if Fig.1, which are formed by Si:P, column 7, rows 11-14). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Jambunathan and disclose wherein the source/drain regions comprise phosphorus doped silicon (Si:P). As disclosed by Jambunathan, the phosphorus doped silicon layer may prevent and protect a source and/or drain electrode from being removed unintentionally, without increasing the channel length or spacer thickness (column 2, rows 14-17).
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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