DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/26/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-9 and 11-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (U.S. Publication No. 2022/0285361 A1; hereinafter Yu) in view of Liu (U.S. Publication No. 2022/0122990 A1)
With respect to claim 1, Yu discloses a method of forming a memory device, the method comprising: depositing a metal stack [510] on a surface comprising a matrix of conductive contacts [521] and insulating dielectric islands [430/440] (see ¶[0093]); etching a portion of the metal stack to expose a top surface of the insulating dielectric islands (See Figure 22-23 ¶[0113-0114], ¶[0117]). Liu fails to disclose depositing a bitline metal stack on a surface comprising a matrix of conductive bitline contacts, depositing a bitline metal layer on the top surface of the exposed insulating dielectric islands and on the bitline metal stack to form a plurality of bitlines. In the same field of endeavor, Liu teaches depositing a bitline metal stack [40] on a surface of conductive bitline contacts [31], depositing a bitline metal layer [60] on the top surface of the exposed insulating dielectric islands [32] and on the bitline metal stack [31] to form a plurality of bitlines (See Figure 6 and ¶[0068]). Implementation of a bitline metal stack and formation of a bitline metal layer to produce a plurality of bitlines as taught by Liu allows for bitlines with good contact performance (see Liu ¶[0055]) and contact area of bitline conducting layers and contact structures may be effectively increased and resistance reduced (See ¶[0071]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 2, the combination of Yu and Liu discloses wherein the bitline metal stack is deposited by physical vapor deposition (PVD) (See Liu ¶[0070]).
With respect to claim 3, the combination of Yu and Liu discloses wherein the bitline metal stack comprises one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WS), or tungsten silicon nitride (WSiN) (see Yu ¶[0043]).
With respect to claim 4, the combination of Yu and Liu discloses wherein the conductive bitline contacts comprise polysilicon (see Yu ¶[0048]).
With respect to claim 5, the combination of Yu and Liu discloses wherein the insulating dielectric islands comprise one or more of an oxide and a nitride (see Yu ¶[0100]).
With respect to claim 6, the combination of Yu and Liu discloses wherein the insulating dielectric islands comprise silicon nitride (SiN) (See Yu ¶[0101]).
With respect to claim 7, the combination of Yu and Liu discloses recessing a portion of the conductive bitline contacts so that the conductive bitline contacts have a height that is less than a height of the insulating dielectric islands prior to depositing the bitline metal stack (See Yu Figure 17 and ¶[0109]).
With respect to claim 8, the combination of Yu and Liu discloses wherein the bitline metal layer comprises one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), or rhenium (Re) (see Liu ¶[0069]).
With respect to claim 9, the combination of Yu and Liu discloses etching a portion of the bitline metal layer (See Yu ¶[0117] and Liu Figure 6 and ¶[0068]).
With respect to claim 11, Yu discloses method of forming a memory device, the method comprising: selectively depositing a metal stack [510] on a surface comprising a matrix of conductive contacts [521] and insulating dielectric islands [430/440] (see ¶[0093]), the metal stack selectively depositing on the conductive contacts relative to the insulating dielectric islands (see Figure 20).
Yu fails to disclose selectively depositing a bitline metal stack on a surface comprising a matrix of conductive bitline contacts and insulating dielectric islands, and depositing a bitline metal layer on a top surface of the insulating dielectric islands and on the bitline metal stack to form a plurality of bitlines.
In the same field of endeavor, Liu teaches selectively depositing a bitline metal stack [40] on a surface comprising a matrix of conductive bitline contacts [31] and depositing a bitline metal layer [60] on a top surface of the insulating dielectric islands [32] and on the bitline metal stack [31] to form a plurality of bitlines (See Figure 6 and ¶[0068]).
Implementation of a bitline metal stack and formation of a bitline metal layer to produce a plurality of bitlines as taught by Liu allows for bitlines with good contact performance (see Liu ¶[0055]) and contact area of bitline conducting layers and contact structures may be effectively increased and resistance reduced (See ¶[0071]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 12, the combination of Yu and Liu discloses recessing a portion of the conductive bitline contacts so that the conductive bitline contacts have a height that is less than a height of the insulating dielectric islands prior to selectively depositing the bitline metal stack (See Yu Figure 17 and ¶[0109]).
With respect to claim 13, the combination of Yu and Liu discloses wherein the bitline metal stack comprises one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WS), or tungsten silicon nitride (WSiN) (see Yu ¶[0043]).
With respect to claim 14, the combination of Yu and Liu discloses wherein the conductive bitline contacts comprise polysilicon (see Yu ¶[0048]).
With respect to claim 15, the combination of Yu and Liu discloses wherein the insulating dielectric islands comprise silicon nitride (SiN) (See Yu ¶[0101]).
With respect to claim 16, the combination of Yu and Liu discloses wherein the bitline metal layer comprises one or more of tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), or rhenium (Re) (see Liu ¶[0069]).
With respect to claim 17, the combination of Yu and Liu discloses etching a portion of the bitline metal layer (See Yu ¶[0117] and Liu Figure 6 and ¶[0068]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Liu as applied to claim 1 above, and further in view of Teo (U.S. Publication No. 2022/0189965 A1)
With respect to claim 10, the combination of Yu and Liu fails to disclose wherein the plurality of bitlines and the conductive bitline contacts are self-aligned.
In the same field of endeavor, Teo teaches wherein the plurality of bitlines and the conductive bitline contacts are self-aligned (See ¶[0085]). Self-aligned bitlines and bitline contacts provide full alignment to provide lower via resistance and capacitance benefits (see Teo ¶[0087]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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