Prosecution Insights
Last updated: October 01, 2026
Application No. 18/614,756

METHOD OF FORMING PACKAGE STRUCTURE

Non-Final OA §102
Filed
Mar 25, 2024
Priority
Sep 26, 2017 — continuation of 10/340,253 +2 more
Examiner
SALERNO, SARAH KATE
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
3 (Non-Final)
74%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
657 granted / 893 resolved
+5.6% vs TC avg
Moderate +15% lift
Without
With
+15.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
34 currently pending
Career history
914
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
57.4%
+17.4% vs TC avg
§102
34.0%
-6.0% vs TC avg
§112
7.2%
-32.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 893 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/6/26 has been entered. Applicant's amendment/arguments filed on 7/6/26 as being acknowledged and entered. By this amendment claims 8, 14, 17, and 20 are canceled, claims 23-24 have been added and claims 1-7, 9-13, 15-16, 18-19 and 21-24. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Teh et al. (US Patent 9,190,380). Claim 1: Teh teaches (Fig. 4A-4G; 6A-6E) a method of forming a package structure, comprising: providing a first die (102A) and a second die (102B); forming a dielectric layer (108A) on the first die and the second die, and patterning the dielectric layer to form a connector opening (128A); electrically connecting a bridge to the first die and the second die through connectors (116A-D) disposed in the connector opening; after electrically connecting the bridge to the first die and the second die, forming an underfill (118) layer in the connector opening between the first die and the bridge as well as between the second die and the bridge to encapsulates the connectors; forming an encapsulant (108B/108C) on the dielectric layer and laterally encapsulating the bridge; and forming a redistribution layer (RDL) structure (Fig. 4G/6E) over the encapsulant and the bridge. Claim 2: Teh teaches (Fig. 6A-6E) a top surface of the bridge is in contact with the RDL structure. Claim 3: Teh teaches (Fig. 4A-4G; 6A-6E) the encapsulant is sandwiched between the dielectric layer and the RDL structure. Claim 4: Teh teaches (Fig. 4A-4G; 6A-6E) wherein the encapsulant and the bridge are sandwiched between the dielectric layer and the RDL structure. Claim 5: Teh teaches (Fig. 4A-4G; 6A-6E) patterning the dielectric layer to form a first opening (124) and a second opening (124) aside the connector opening, wherein the first opening exposes a first connector of the first die, and the second opening exposes a second connector of the second die. Claim 9: Teh teaches (Fig. 4A-4G; 6A-6E) the underfill layer separates the connectors from the dielectric layer Allowable Subject Matter Claims 6-7, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach the physical relationship between the underfill, encapsulant and dielectric layer described in these claims. The prior art of record does not teach the claimed combination of the dielectric layer, underfill, and encapsulant and they relationship to the die and bridge. Claims 11-13, 15-16, 18-19 and 21-24 are allowable over the prior art. Regarding, both claims, added underlined limitations in conjunction with the previously presented subject matter are not taught by the prior art of record. Response to Arguments Applicant’s arguments with respect to claim(s) 1-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at 5712721705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SARAH K SALERNO/Primary Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Mar 25, 2024
Application Filed
Nov 21, 2025
Non-Final Rejection (signed) — §102
Jan 05, 2026
Non-Final Rejection mailed — §102
Apr 02, 2026
Response Filed
Apr 24, 2026
Final Rejection mailed — §102
Jul 06, 2026
Request for Continued Examination
Jul 10, 2026
Response after Non-Final Action
Sep 24, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12749798
WIRELESS INTERCONNECTS IN INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES
3y 3m to grant Granted Sep 29, 2026
Patent 12751011
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING COMPOSITE DIELECTRIC ISOLATION STRUCTURE IN A STAIRCASE REGION AND METHODS OF FORMING THE SAME
3y 2m to grant Granted Sep 29, 2026
Patent 12751012
MEMORY DEVICES AND RELATED ELECTRONIC SYSTEMS
2y 10m to grant Granted Sep 29, 2026
Patent 12742240
SEMICONDUCTOR MANUFACTURING APPARATUS, GAS SUPPLYING METHOD USING THE SAME, AND SEMICONDUCTOR MANUFACTURING METHOD USING THE SAME
3y 1m to grant Granted Sep 22, 2026
Patent 12736497
BIOCHIP AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
74%
Grant Probability
89%
With Interview (+15.0%)
2y 11m (~5m remaining)
Median Time to Grant
High
PTA Risk
Based on 893 resolved cases by this examiner. Grant probability derived from career allowance rate.

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