Prosecution Insights
Last updated: April 19, 2026
Application No. 18/615,403

GATE STRUCTURE AND PATTERNING METHOD

Non-Final OA §102
Filed
Mar 25, 2024
Examiner
OH, JAEHWAN
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
2 (Non-Final)
85%
Grant Probability
Favorable
2-3
OA Rounds
2y 4m
To Grant
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
555 granted / 656 resolved
+16.6% vs TC avg
Moderate +10% lift
Without
With
+10.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
23 currently pending
Career history
679
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
47.4%
+7.4% vs TC avg
§102
36.8%
-3.2% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 656 resolved cases

Office Action

§102
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bao et al. (U.S. Patent Application Publication 2020/0118888, hereinafter referred to as Bao). As to claim 1, Bao teaches 1. A device, comprising: a semiconductor substrate; a first semiconductor fin structure that protrudes vertically out of the substrate; a first work function metal (WFM) structure disposed over the first semiconductor fin structure, wherein the first WFM structure has a first thickness and has a first number of sub-layers; a second semiconductor fin structure that protrudes vertically out of the substrate; and a second WFM structure disposed over the second semiconductor fin structure, wherein the second WFM structure has a second thickness and has a second number of sub-layers; wherein: the first thickness is different from the second thickness; or the second number of sub-layers is different from the first number of sub-layers. [see Fig. 15 for example; ¶0050~0053] As to claim 2, Bao teaches 2. The device of claim 1, wherein: the first semiconductor fin structure includes a p-type channel; and the second semiconductor fin structure includes an n-type channel. [see 210 and 240 in Fig. 15 for example] As to claim 3, Bao teaches 3. The device of claim 2, wherein the first thickness is less than the second thickness. [see 210 and 240 in Fig. 15 for example] As to claim 4, Bao teaches 4. The device of claim 2, wherein the first number of sub-layers is less than the second number of sub-layers. [see 210 and 240 in Fig. 15 for example] As to claim 5, Bao teaches 5. The device of claim 4, wherein: the second WFM structure includes a first sub-layer and a second sub-layer; and the first WFM structure includes the first sub-layer but not the second sub-layer. [see 210 and 240 in Fig. 15 for example] As to claim 6, Bao teaches 6. The device of claim 5, wherein: the first sub-layer is a p-type WFM sub-layer; and the second sub-layer is an n-type WFM sub-layer. [see 210 and 240 in Fig. 15 for example] As to claim 7, Bao teaches 7. The device of claim 1, further comprising: a third semiconductor fin structure that protrudes vertically out of the substrate; and a third work WFM structure disposed over the third semiconductor fin structure, wherein: the third WFM structure has a third thickness and has a third number of sub-layers; the third thickness is different from the second thickness and the first thickness; or the third number of sub-layers is different from the second number of sub-layers and the second number of sub-layers. [see 220, 230, 250 and 260 in Fig. 15 for example] As to claim 8, Bao teaches 8. The device of claim 7, wherein the third thickness is greater than the second thickness and the first thickness. [see 220, 230, 250 and 260 in Fig. 15 for example] As to claim 9, Bao teaches 9. The device of claim 7, wherein the third number of sub-layers is greater than the second number of sub-layers and the first number of sub-layers. [see 220, 230, 250 and 260 in Fig. 15 for example] As to claim 10, Bao teaches 10. The device of claim 7, wherein: the first WFM structure, the second WFM structure, and the third WFM structure each contains a first p-type WFM sub-layer; the third WFM structure and the second WFM structure, but not the first WFM structure, each contains an n-type WFM sub-layer; and the third WFM structure, but not the first WFM structure or the second WFM structure, contains a second p-type WFM sub-layer different from the first p-type WFM sub-layer. [see 220, 230, 250 and 260 in Fig. 15 for example] As to claim 11, Bao teaches 11. The device of claim 7, wherein the third semiconductor fin structure has a same type of conductivity as the second semiconductor fin structure but a different type of conductivity than the first semiconductor fin structure. [see 220, 230, 250 and 260 in Fig. 15 for example] As to claim 12, Bao teaches 12. The device of claim 1, further comprising a fill metal structure disposed over both the first WFM structure and the second WFM structure. [see 1402A in Fig. 15 for example] As to claim 13, Bao teaches 13. A device, comprising: a semiconductor substrate; a first channel that protrudes vertically out of the substrate; a first work function metal (WFM) structure disposed over the first channel, wherein the first WFM structure includes a p-type WFM layer; a second channel that protrudes vertically out of the substrate; a second WFM structure disposed over the second channel, wherein the second channel includes the p-type WFM layer and an n-type WFM layer, and wherein no portion of the n-type WFM layer is located in the first WFM structure; and a fill metal structure disposed over both the first WFM structure and the second WFM structure. [see 220, 230, 250 and 260 in Fig. 15 for example] As to claim 14, Bao teaches 14. The device of claim 13, wherein the p-type WFM layer is a first p-type WFM layer, and wherein the device further comprises: a third channel that protrudes vertically out of the substrate; a third WFM structure disposed over the third channel, wherein the third channel includes the first p-type WFM layer, the n-type WFM layer, and a second p-type WFM layer different from the first p-type WFM layer, and wherein no portion of the second p-type WFM layer is located in the first WFM structure or in the second WFM structure. [see 220, 230, 250 and 260 in Fig. 15 for example] As to claim 15, Bao teaches 15. The device of claim 14, wherein: the first channel is a p-type channel; and the second channel and the third channel are n-type channels. [see 220, 230, 250 and 260 in Fig. 15 for example] As to claim 16, Bao teaches 16. The device of claim 14, wherein the third channel is located between the first channel and the second channel in a cross-sectional side view. [see 220, 230, 250 and 260 in Fig. 15 for example] As to claim 17, Bao teaches 17. The device of claim 13, wherein: the fill metal structure is in direct contact with the p-type WFM layer; and the n-type WFM layer is disposed below the p-type WFM layer. [see 220, 230, 250 and 260 in Fig. 15 for example] As to claim 18, Bao teaches 18. A device, comprising: a semiconductor substrate; a first semiconductor fin structure that protrudes vertically out of the substrate; a first work function metal (WFM) structure disposed over the first semiconductor fin structure, wherein the first WFM structure has a first thickness and has a first number of sub-layers; a second semiconductor fin structure that protrudes vertically out of the substrate; a second WFM structure disposed over the second semiconductor fin structure, wherein the second WFM structure has a second thickness and has a second number of sub-layers; a third semiconductor fin structure that protrudes vertically out of the substrate; a third WFM structure disposed over the second semiconductor fin structure, wherein the third WFM structure has a third thickness and has a third number of sub-layers; wherein: the third thickness is greater than the second thickness; the second thickness is greater than the first thickness; the third number of sub-layers is greater than the second number of sub-layers; and the second number of sub-layers is greater than the first number of sub-layers. [see 220, 230, 250 and 260 in Fig. 15 for example] As to claim 19, Bao teaches 19. The device of claim 18, wherein an n-type WFM layer is implemented in the second WFM structure and the third WFM structure, but not in the first WFM structure. [see 220, 230, 250 and 260 in Fig. 15 for example] As to claim 20, Bao teaches 20. The device of claim 18, wherein a glue metal layer is implemented as a topmost one of the sub-layers in each of the first WFM structure, the second WFM structure, and the third WFM structure. [see 1402A in Fig. 15 for example] Conclusion Claims 1-20 are rejected as explained above. The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAEHWAN OH whose telephone number is (571) 270-5800. The examiner can normally be reached on Monday - Friday 9:00 AM-5:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAEHWAN OH/ Primary Examiner, Art Unit 2899
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Prosecution Timeline

Mar 25, 2024
Application Filed
Oct 03, 2025
Non-Final Rejection — §102
Jan 07, 2026
Response Filed
Apr 10, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+10.4%)
2y 4m
Median Time to Grant
Moderate
PTA Risk
Based on 656 resolved cases by this examiner. Grant probability derived from career allow rate.

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